Resources Contact Us Home
Browse by Category: Main > Physics
Class Information
Number: 257/E29.155
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Semiconductors devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (epo) > Electrodes (epo) > Of specified material (epo) > Electrodes for igfet (epo) > Silicon gate conductor material (epo) > Multiple silicon layers
Description: This subclass is indented under subclass E29.154. This subclass is substantially the same in scope as ECLA classification H01L29/49C2

Sub-classes under this class:

Class Number Class Name Patents
257/E29.157 Including barrier layer between silicon and non-si electrode 242
257/E29.156 Including silicide layer contacting silicon layer (epo) 358

Patents under this class:
1 2 3 4

Patent Number Title Of Patent Date Issued
8609479 Gated-varactors Dec. 17, 2013
8373221 Nanocluster charge storage device Feb. 12, 2013
8278644 Switching device and nonvolatile memory device Oct. 2, 2012
8237221 Semiconductor device and method of manufacturing semiconductor device Aug. 7, 2012
8148730 Semiconductor device and method for manufacturing semiconductor device Apr. 3, 2012
7960256 Use of CL2 and/or HCL during silicon epitaxial film formation Jun. 14, 2011
7960764 Semiconductor device manufacturing method and semiconductor device Jun. 14, 2011
7851847 Flash memory device and method of erasing the same Dec. 14, 2010
7714366 CMOS transistor with a polysilicon gate electrode having varying grain size May. 11, 2010
7566644 Method for forming gate electrode of semiconductor device Jul. 28, 2009
7557403 Double gate transistors having at least two polysilicon patterns on a thin body used as active region and methods of forming the same Jul. 7, 2009
7075145 Poly-sealed silicide trench gate Jul. 11, 2006
7042055 Semiconductor device and manufacturing thereof May. 9, 2006
7026218 Use of indium to define work function of p-type doped polysilicon Apr. 11, 2006
7009253 Method and apparatus for preventing microcircuit thermo-mechanical damage during an ESD event Mar. 7, 2006
6995434 Semiconductor device and method of fabricating the same Feb. 7, 2006
6991999 Bi-layer silicon film and method of fabrication Jan. 31, 2006
6982433 Gate-induced strain for MOS performance improvement Jan. 3, 2006
6972232 Method of manufacturing a semiconductor device Dec. 6, 2005
6969888 Planarized and silicided trench contact Nov. 29, 2005
6967384 Structure and method for ultra-small grain size polysilicon Nov. 22, 2005
6963100 Semiconductor device having gate electrode in which depletion layer can be generated Nov. 8, 2005
6958275 MOSFET power transistors and methods Oct. 25, 2005
6911384 Gate structure with independently tailored vertical doping profile Jun. 28, 2005
6893948 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size May. 17, 2005
6875676 Methods for producing a highly doped electrode for a field effect transistor Apr. 5, 2005
6872972 Method for forming silicon film with changing grain size by thermal process Mar. 29, 2005
6861701 Trench power MOSFET with planarized gate bus Mar. 1, 2005
6849899 High speed trench DMOS Feb. 1, 2005
6838695 CMOS device structure with improved PFET gate electrode Jan. 4, 2005
6821868 Method of forming nitrogen enriched gate dielectric with low effective oxide thickness Nov. 23, 2004
6809017 Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication Oct. 26, 2004
6803611 Use of indium to define work function of p-type doped polysilicon Oct. 12, 2004
6794714 Transistor and method for fabricating the same Sep. 21, 2004
6791141 Semiconductor constructions comprising stacks with floating gates therein Sep. 14, 2004
6780741 Method of forming a novel gate electrode structure comprised of a silicon-germanium layer located between random grained polysilicon layers Aug. 24, 2004
6762454 Stacked polysilicon layer for boron penetration inhibition Jul. 13, 2004
6730976 Multilayer gate electrode structure with tilted on implantation May. 4, 2004
6720626 Semiconductor device having improved gate structure Apr. 13, 2004
6703672 Polysilicon/amorphous silicon composite gate electrode Mar. 9, 2004
6693313 Field effect transistors, field effect transistor assemblies, and integrated circuitry Feb. 17, 2004
6686637 Gate structure with independently tailored vertical doping profile Feb. 3, 2004
6682992 Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures Jan. 27, 2004
6670263 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size Dec. 30, 2003
6653699 Polysilicon/Amorphous silicon gate structures for integrated circuit field effect transistors Nov. 25, 2003
6649518 Method of forming a conductive contact Nov. 18, 2003
6642592 Semiconductor device and method for fabricating same Nov. 4, 2003
6627951 High speed trench DMOS Sep. 30, 2003
6620713 Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication Sep. 16, 2003
6620671 Method of fabricating transistor having a single crystalline gate conductor Sep. 16, 2003

1 2 3 4

  Recently Added Patents
Method and system for controlled media sharing in a network
Toy track intersection component
Systems and methods for restoring images
Light emitting device power supply circuit, and light emitting device driver circuit and control method thereof
System and method for deriving cell global identity information
Method and apparatus for monitoring wireless communication in hearing assistance systems
Liquid crystal display apparatus
  Randomly Featured Patents
Magnetic field sensing device
Device for purposely influencing the longitudinal curvature of a ski
Method for masking DQ bits
Hot melt spray cladding of innerduct liner
Gearing without backlash for electric power steering
Divider and mixer circuit having the same
Method and apparatus for determining mask layouts for a spacer-is-dielectric self-aligned double-patterning process
Treatment of diseases mediated by the nitric oxide/cGMP/protein kinase G pathway
Paper pallet for four-wheeled motorcycle
Composite semipermeable membrane of polyamine and trianzine