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Class Information
Number: 257/E29.146
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Semiconductors devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (epo) > Electrodes (epo) > Of specified material (epo) > Ohmic electrodes (epo) > On silicon (epo)
Description: This subclass is indented under subclass E29.143. This subclass is substantially the same in scope as ECLA classification H01L29/45S.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7479417 |
Method for manufacturing contact structure of pixel electrode of liquid crystal display device |
Jan. 20, 2009 |
| 7452777 |
Self-aligned trench MOSFET structure and method of manufacture |
Nov. 18, 2008 |
| 7075145 |
Poly-sealed silicide trench gate |
Jul. 11, 2006 |
| 7052963 |
Method of forming trench transistor with chained implanted body including a plurality of implantation with different energies |
May. 30, 2006 |
| 7041538 |
Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS |
May. 9, 2006 |
| 7037827 |
Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same |
May. 2, 2006 |
| 7037829 |
Compound structure for reduced contact resistance |
May. 2, 2006 |
| 7038318 |
Compound structure for reduced contact resistance |
May. 2, 2006 |
| 7023030 |
MISFET |
Apr. 4, 2006 |
| 7015125 |
Trench MOSFET device with polycrystalline silicon source contact structure |
Mar. 21, 2006 |
| 7009253 |
Method and apparatus for preventing microcircuit thermo-mechanical damage during an ESD event |
Mar. 7, 2006 |
| 6987040 |
Trench MOSFET with increased channel density |
Jan. 17, 2006 |
| 6984864 |
Semiconductor device with MISFET having low leakage current |
Jan. 10, 2006 |
| 6972460 |
Semiconductor device and manufacturing method thereof |
Dec. 6, 2005 |
| 6969888 |
Planarized and silicided trench contact |
Nov. 29, 2005 |
| 6958515 |
N-channel LDMOS with buried p-type region to prevent parasitic bipolar effects |
Oct. 25, 2005 |
| 6955978 |
Uniform contact |
Oct. 18, 2005 |
| 6953968 |
High voltage withstanding semiconductor device |
Oct. 11, 2005 |
| 6946371 |
Methods of fabricating semiconductor structures having epitaxially grown source and drain elements |
Sep. 20, 2005 |
| 6943367 |
Thin film transistor array panel |
Sep. 13, 2005 |
| 6933589 |
Method of making a semiconductor transistor |
Aug. 23, 2005 |
| 6927101 |
Field-effect-controllable semiconductor component and method for fabricating the component |
Aug. 9, 2005 |
| 6924198 |
Self-aligned trench transistor using etched contact |
Aug. 2, 2005 |
| 6908849 |
High aspect ratio contact structure with reduced silicon consumption |
Jun. 21, 2005 |
| 6903416 |
Trench transistors and methods for fabricating trench transistors |
Jun. 7, 2005 |
| 6888196 |
Vertical MOSFET reduced in cell size and method of producing the same |
May. 3, 2005 |
| 6878586 |
Semiconductor memory device |
Apr. 12, 2005 |
| 6878999 |
Transistor with improved safe operating area |
Apr. 12, 2005 |
| 6870218 |
Integrated circuit structure with improved LDMOS design |
Mar. 22, 2005 |
| 6861701 |
Trench power MOSFET with planarized gate bus |
Mar. 1, 2005 |
| 6858904 |
High aspect ratio contact structure with reduced silicon consumption |
Feb. 22, 2005 |
| 6858500 |
Semiconductor device and its manufacturing method |
Feb. 22, 2005 |
| 6858484 |
Method of fabricating semiconductor integrated circuit device |
Feb. 22, 2005 |
| 6849899 |
High speed trench DMOS |
Feb. 1, 2005 |
| 6841879 |
Semiconductor device |
Jan. 11, 2005 |
| 6833556 |
Insulated gate field effect transistor having passivated schottky barriers to the channel |
Dec. 21, 2004 |
| 6822288 |
Trench MOSFET device with polycrystalline silicon source contact structure |
Nov. 23, 2004 |
| 6818946 |
Trench MOSFET with increased channel density |
Nov. 16, 2004 |
| 6815767 |
Insulated gate transistor |
Nov. 9, 2004 |
| 6812086 |
Method of making a semiconductor transistor |
Nov. 2, 2004 |
| 6794713 |
Semiconductor device and method of manufacturing the same including a dual layer raised source and drain |
Sep. 21, 2004 |
| 6791149 |
Diffusion barrier layer for semiconductor wafer fabrication |
Sep. 14, 2004 |
| 6784471 |
Semiconductor device and manufacturing method thereof |
Aug. 31, 2004 |
| 6784114 |
Monatomic layer passivation of semiconductor surfaces |
Aug. 31, 2004 |
| 6756274 |
Fabrication process for a super-self-aligned trench-gated DMOS with reduced on-resistance |
Jun. 29, 2004 |
| 6750507 |
Super-self-aligned trench-gated DMOS with reduced on-resistance |
Jun. 15, 2004 |
| 6746952 |
Diffusion barrier layer for semiconductor wafer fabrication |
Jun. 8, 2004 |
| 6747321 |
Semiconductor memory device with a silicide layer formed on regions other than source regions |
Jun. 8, 2004 |
| 6727127 |
Laterally diffused MOS transistor (LDMOS) and method of making same |
Apr. 27, 2004 |
| 6720258 |
Method of fabricating a nickel silicide on a substrate |
Apr. 13, 2004 |
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