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Class Information
Number: 257/E29.108
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Semiconductors devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (epo) > Electrical characteristics due to properties of entire semiconductor body rather than just surface region (epo) > Characterized by physical imperfections; having polished or roughened surface (epo) > Imperfections on surface of semiconductor body (epo)
Description: This subclass is indented under subclass E29.106. This subclass is substantially the same in scope as ECLA classification H01L29/34.










Patents under this class:

Patent Number Title Of Patent Date Issued
8592949 Method of texturing the surface of a silicon substrate, and textured silicon substrate for a solar cell Nov. 26, 2013
8299462 Constructions comprising hafnium oxide and/or zirconium oxide Oct. 30, 2012
8187983 Methods for fabricating semiconductor components using thinning and back side laser processing May. 29, 2012
8044492 Compound semiconductor device including AIN layer of controlled skewness Oct. 25, 2011
7989321 Semiconductor device gate structure including a gettering layer Aug. 2, 2011
7884446 Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate Feb. 8, 2011
7855428 Conductive liner at an interface between a shallow trench isolation structure and a buried oxide layer Dec. 21, 2010
7737004 Multilayer gettering structure for semiconductor device and method Jun. 15, 2010
7655950 Method of manufacturing an active matrix substrate and an image display device using the same Feb. 2, 2010
7545004 Method and structure for forming strained devices Jun. 9, 2009
7459767 Semiconductor device including semiconductor memory element and method for producing same Dec. 2, 2008
7388278 High performance field effect transistors on SOI substrate with stress-inducing material as buried insulator and methods Jun. 17, 2008
7064033 Semiconductor device and method of manufacturing same Jun. 20, 2006
6949434 Method of manufacturing a vertical semiconductor device Sep. 27, 2005
6927167 Method for manufacturing semiconductor device having controlled surface roughness Aug. 9, 2005
6903417 Power semiconductor device Jun. 7, 2005
6812523 Semiconductor wafer with ultra thin doping level formed by defect engineering Nov. 2, 2004
6707130 Bipolar device with polycrystalline film contact and resistance Mar. 16, 2004
6649478 Semiconductor device and method of manufacturing same Nov. 18, 2003
6498366 Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode Dec. 24, 2002
6229196 Semiconductor device and fabrication method thereof May. 8, 2001
6165872 Semiconductor device and its manufacturing method Dec. 26, 2000
5994187 Method of manufacturing a vertical semiconductor device Nov. 30, 1999
5986315 Guard wall to reduce delamination effects within a semiconductor die Nov. 16, 1999
5939770 Semiconductor device and its manufacturing method Aug. 17, 1999
5773362 Method of manufacturing an integrated ULSI heatsink Jun. 30, 1998
5729052 Integrated ULSI heatsink Mar. 17, 1998
5689130 Vertical semiconductor device with ground surface providing a reduced ON resistance Nov. 18, 1997
5663096 Method of manufacturing a vertical semiconductor device with ground surface providing a reduced ON resistance Sep. 2, 1997
5502668 Semiconductor memory device capable of low-voltage programming Mar. 26, 1996
5304828 Silicon layer having increased surface area and method for manufacturing Apr. 19, 1994
5270256 Method of forming a guard wall to reduce delamination effects Dec. 14, 1993
5242862 Semiconductor device and method of manufacturing same Sep. 7, 1993
5149676 Silicon layer having increased surface area and method for manufacturing Sep. 22, 1992
4797724 Reducing bipolar parasitic effects in IGFET devices Jan. 10, 1989











 
 
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