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Class Information
Number: 257/E29.043
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Semiconductors devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (epo) > Electrical characteristics due to properties of entire semiconductor body rather than just surface region (epo) > Characterized by specified shape or size of pn junction or by specified impurity concentration gradient within the device (epo) > With semiconductor regions connected to electrode not carrying current to be rectified, amplified or switched and such electrode being part of semiconductor device which comprises three or more electrodes (epo)
Description: This subclass is indented under subclass E29.005. This subclass is substantially the same in scope as ECLA classification H01L29/10.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7422970 |
Method for modifying circuit within substrate |
Sep. 9, 2008 |
| 7423332 |
Vertical laminated electrical switch circuit |
Sep. 9, 2008 |
| 7211865 |
Silicided body contact SOI device |
May. 1, 2007 |
| 6946364 |
Integrated circuit having a device wafer with a diffused doped backside layer |
Sep. 20, 2005 |
| 6867495 |
Integrated circuit having a device wafer with a diffused doped backside layer |
Mar. 15, 2005 |
| 6362075 |
Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide |
Mar. 26, 2002 |
| 6255693 |
Ion implantation with programmable energy, angle, and beam current |
Jul. 3, 2001 |
| 6229148 |
Ion implantation with programmable energy, angle, and beam current |
May. 8, 2001 |
| 6225674 |
Semiconductor structure and method of manufacture |
May. 1, 2001 |
| 6111281 |
Solid-state image-pickup device and MOS transistor having a reduced incidental capacitance |
Aug. 29, 2000 |
| 5599389 |
Compound semiconductor and method of manufacturing the same |
Feb. 4, 1997 |
| 5196908 |
Micro MIS type FET and manufacturing process therefor |
Mar. 23, 1993 |
| 5155568 |
High-voltage semiconductor device |
Oct. 13, 1992 |
| 5034335 |
Method of manufacturing a silicon on insulator (SOI) semiconductor device |
Jul. 23, 1991 |
| 4936928 |
Semiconductor device |
Jun. 26, 1990 |
| 4937648 |
Resistant transistor |
Jun. 26, 1990 |
| 4903091 |
Heterojunction transistor having bipolar characteristics |
Feb. 20, 1990 |
| 4902633 |
Process for making a bipolar integrated circuit |
Feb. 20, 1990 |
| 4887144 |
Topside substrate contact in a trenched semiconductor structure and method of fabrication |
Dec. 12, 1989 |
| 4864377 |
Silicon on insulator (SOI) semiconductor device |
Sep. 5, 1989 |
| H569 |
Charge storage depletion region discharge protection |
Jan. 3, 1989 |
| 4757027 |
Method for fabricating improved oxide defined transistors |
Jul. 12, 1988 |
| 4727403 |
Double heterojunction semiconductor device with injector |
Feb. 23, 1988 |
| 4633279 |
Semiconductor devices |
Dec. 30, 1986 |
| 4442445 |
Planar doped barrier gate field effect transistor |
Apr. 10, 1984 |
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