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Class Information
Number: 257/E27.105
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Device consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate, e.g., integrated circuit device (epo) > Including semiconductor component with at least one potential barrier or surface barrier adapted for rectifying, oscillating, amplifying, or switching, or including integrated passive circuit elements (epo) > With semiconductor substrate only (epo) > Including a plurality of individual components in a repetitive configuration (epo) > Masterslice integrated circuit (epo)
Description: This subclass is indented under subclass E27.07. This subclass is substantially the same in scope as ECLA classification H01L27/118.

Sub-classes under this class:

Class Number Class Name Patents
257/E27.11 Input and output buffer/driver (epo) 167
257/E27.106 Using bipolar structure (epo) 54
257/E27.109 Using combined field-effect/bipolar structure (epo) 46
257/E27.107 Using field-effect structure (epo) 126

Patents under this class:
1 2 3 4 5 6

Patent Number Title Of Patent Date Issued
8710553 Method and apparatus for connecting signal lines of multiple layers to certain contacts while preventing connections with other contacts Apr. 29, 2014
8569860 Semiconductor devices having line type active regions and methods of fabricating the same Oct. 29, 2013
8563986 Power semiconductor devices having selectively doped JFET regions and related methods of forming such devices Oct. 22, 2013
8482039 Memory and interconnect design in fine pitch Jul. 9, 2013
8441040 Semiconductor memory device May. 14, 2013
8354696 Semiconductor device and layout design apparatus of semiconductor device Jan. 15, 2013
8319277 Semiconductor device, method of manufacturing same, and apparatus for designing same Nov. 27, 2012
8278689 Memory and interconnect design in fine pitch Oct. 2, 2012
8124429 Reprogrammable circuit board with alignment-insensitive support for multiple component contact types Feb. 28, 2012
8105900 Manufacturing method of non-volatile memory Jan. 31, 2012
8022443 Memory and interconnect design in fine pitch Sep. 20, 2011
7960833 Integrated circuits and interconnect structure for integrated circuits Jun. 14, 2011
7906800 Semiconductor integrated circuit Mar. 15, 2011
7893518 Method for generating a layout, use of a transistor layout, and semiconductor circuit Feb. 22, 2011
7825475 Mixed voltage tolerant input/output electrostatic discharge devices Nov. 2, 2010
7781804 Non-volatile memory Aug. 24, 2010
7755110 Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone Jul. 13, 2010
7696541 Structure for a latchup robust gate array using through wafer via Apr. 13, 2010
7683401 Semiconductor device and method of fabricating thereof capable of reducing a shallow trench isolation stress influence by utilizing layout pattern designs Mar. 23, 2010
7582921 Semiconductor device and method for patterning Sep. 1, 2009
7521735 Multiple layer and crystal plane orientation semiconductor substrate Apr. 21, 2009
7476915 Semiconductor integrated circuit including a first region and a second region Jan. 13, 2009
7411277 Semiconductor integrated circuit having shield wiring Aug. 12, 2008
7348610 Multiple layer and crystal plane orientation semiconductor substrate Mar. 25, 2008
7265448 Interconnect structure for power transistors Sep. 4, 2007
7148514 Nitride semiconductor light emitting diode and fabrication method thereof Dec. 12, 2006
7075334 Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks Jul. 11, 2006
7071734 Programmable logic devices with silicon-germanium circuitry and associated methods Jul. 4, 2006
7062742 Routing structure for transceiver core Jun. 13, 2006
7058863 Semiconductor integrated circuit Jun. 6, 2006
7053653 Inter-tile buffer system for a field programmable gate array May. 30, 2006
7053424 Semiconductor integrated circuit device and its manufacture using automatic layout May. 30, 2006
7051308 Method and apparatus for integrated circuit design with library cells May. 23, 2006
7049930 Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor device including at least one such arrangement May. 23, 2006
7047514 Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign May. 16, 2006
7043713 Implementing programmable logic array embedded in mask-programmed ASIC May. 9, 2006
7000165 Configurable memory design for masked programmable logic Feb. 14, 2006
6989687 Customizable and programmable cell array Jan. 24, 2006
6985012 Customizable and programmable cell array Jan. 10, 2006
6974978 Gate array architecture Dec. 13, 2005
6948145 Tool suite for the rapid development of advanced standard cell libraries employing the connection properties of nets to identify potential pin placements Sep. 20, 2005
6941534 Semiconductor device and layout data generation apparatus Sep. 6, 2005
6930511 Array of programmable cells with customized interconnections Aug. 16, 2005
6920067 Integrated circuit embedded with single-poly non-volatile memory Jul. 19, 2005
6885043 ASIC routing architecture Apr. 26, 2005
6868530 Method for fabricating an integrated semiconductor circuit Mar. 15, 2005
6819594 Electrically erasable programmable logic device Nov. 16, 2004
6819136 Customizable and programmable cell array Nov. 16, 2004
6800884 Inter-tile buffer system for a field programmable gate array Oct. 5, 2004

1 2 3 4 5 6

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