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Class Information
Number: 257/E27.099
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Device consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate, e.g., integrated circuit device (epo) > Including semiconductor component with at least one potential barrier or surface barrier adapted for rectifying, oscillating, amplifying, or switching, or including integrated passive circuit elements (epo) > With semiconductor substrate only (epo) > Including a plurality of individual components in a repetitive configuration (epo) > Including field-effect component (epo) > Static random access memory, sram, structure (epo) > Load element being a mosfet transistor (epo)
Description: OLE_LINK1This subclass is indented under subclass E27.098. This subclass is substantially the same in scope as ECLA classification OLE_LINK1 H01L27/11F.

Sub-classes under this class:

Class Number Class Name Patents
257/E27.1 Load element being a thin film transistor (epo) 392

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13

Patent Number Title Of Patent Date Issued
6160298 Full CMOS SRAM cell comprising Vcc and Vss buses on both sides of each of complementary data lines on a single level Dec. 12, 2000
6157564 Semiconductor device Dec. 5, 2000
6147385 CMOS static random access memory devices Nov. 14, 2000
6144073 Monolithically-integrated static random access memory device Nov. 7, 2000
6133608 SOI-body selective link method and apparatus Oct. 17, 2000
6133084 Method of fabricating static random access memory Oct. 17, 2000
6127209 Semiconductor device and method of manufacturing the same Oct. 3, 2000
6127704 Structure of SRAM cell and method for fabricating the same Oct. 3, 2000
6118158 Static random access memory device having a memory cell array region in which a unit cell is arranged in a matrix Sep. 12, 2000
6104233 Substrate structure of semi-conductor device Aug. 15, 2000
6100128 Process for making six-transistor SRAM cell local interconnect structure Aug. 8, 2000
6101120 Semiconductor memory device Aug. 8, 2000
6100185 Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line Aug. 8, 2000
6100568 Semiconductor device including a memory cell and peripheral portion and method for forming same Aug. 8, 2000
6097103 Semiconductor device having an improved interconnection and method for fabricating the same Aug. 1, 2000
6097073 Triangular semiconductor or gate Aug. 1, 2000
6093602 Method to form polycide local interconnects between narrowly-spaced features while eliminating stringers Jul. 25, 2000
6090673 Device contact structure and method for fabricating same Jul. 18, 2000
6090654 Method for manufacturing a static random access memory cell Jul. 18, 2000
6091095 Semiconductor storage Jul. 18, 2000
6091628 Static random access memory device and method of manufacturing the same Jul. 18, 2000
6091630 Radiation hardened semiconductor memory Jul. 18, 2000
6081016 CMOS device with improved wiring density Jun. 27, 2000
6081444 Static memory adopting layout that enables minimization of cell area Jun. 27, 2000
6065973 Memory cell having active regions without N+ implants May. 23, 2000
6037202 Method for growing an epitaxial layer of material using a high temperature initial growth phase and a low temperature bulk growth phase Mar. 14, 2000
6037638 Semiconductor memory device Mar. 14, 2000
6038164 SRAM cell configuration and method for its fabrication Mar. 14, 2000
6031267 Compact static RAM cell Feb. 29, 2000
6030548 SRAM memory device having reduced size Feb. 29, 2000
6031271 High yield semiconductor device and method of fabricating the same Feb. 29, 2000
6025253 Differential poly-edge oxidation for stable SRAM cells Feb. 15, 2000
6015996 Cell structure of an improved CMOS static RAM and its fabrication method Jan. 18, 2000
6016390 Method and apparatus for eliminating bitline voltage offsets in memory devices Jan. 18, 2000
6011712 Interconnection structures for integrated circuits including recessed conductive layers Jan. 4, 2000
6008080 Method of making a low power SRAM Dec. 28, 1999
6005797 Latch-up prevention for memory cells Dec. 21, 1999
RE36440 Integrated circuit SRAM cell layouts Dec. 14, 1999
6001680 Static random memory device Dec. 14, 1999
5994735 Semiconductor device having a vertical surround gate metal-oxide semiconductor field effect transistor, and manufacturing method thereof Nov. 30, 1999
5989951 Semiconductor device with contacts formed in self-alignment Nov. 23, 1999
5979784 Method of forming local interconnection of a static random access memory Nov. 9, 1999
5981995 Static random access memory cell having buried sidewall transistors, buried bit lines, and buried vdd and vss nodes Nov. 9, 1999
5977638 Edge metal for interconnect layers Nov. 2, 1999
5973376 Architecture having diamond shaped or parallelogram shaped cells Oct. 26, 1999
5966317 Shielded bitlines for static RAMs Oct. 12, 1999
5960278 Method of manufacturing SRAM cell Sep. 28, 1999
5955746 SRAM having enhanced cell ratio Sep. 21, 1999
5956585 Method of forming a self-aligned damage-free buried contact Sep. 21, 1999
5955768 Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell Sep. 21, 1999

1 2 3 4 5 6 7 8 9 10 11 12 13

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