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Class Information
Number: 257/E27.076
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Device consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate, e.g., integrated circuit device (epo) > Including semiconductor component with at least one potential barrier or surface barrier adapted for rectifying, oscillating, amplifying, or switching, or including integrated passive circuit elements (epo) > With semiconductor substrate only (epo) > Including a plurality of individual components in a repetitive configuration (epo) > Including bipolar component (epo) > Including bipolar transistor (epo) > Array of single bipolar transistors only, e.g. read only memory structure (epo)
Description: This subclass is indented under subclass E27.074. This subclass is substantially the same in scope as ECLA classification H01L27/102T4.










Patents under this class:

Patent Number Title Of Patent Date Issued
8546888 Isolation regions Oct. 1, 2013
8390097 Insulated gate bipolar transistor having contact region with variable width Mar. 5, 2013
8362535 Layout structure of non-volatile memory device Jan. 29, 2013
7872326 Array of vertical bipolar junction transistors, in particular selectors in a phase change memory device Jan. 18, 2011
7847373 Fabricating bipolar junction select transistors for semiconductor memories Dec. 7, 2010
7649259 Semiconductor device including a plurality of wiring lines Jan. 19, 2010
7622756 Semiconductor device and radio communication device Nov. 24, 2009
7317240 Redundant interconnect high current bipolar device and method of forming the device Jan. 8, 2008
7312497 Fabrication of conductive lines interconnecting first conductive gates in nonvolatile memories having second conductive gates provided by conductive gate lines, wherein the adjacent conductive Dec. 25, 2007
7276762 NROM flash memory devices on ultrathin silicon Oct. 2, 2007
6768667 Semiconductor memory device Jul. 27, 2004
5097316 Complementary NPN and PNP lateral transistors separated from substrate by intersecting slots filled with substrate oxide for minimal interference therefrom Mar. 17, 1992
4859930 Current source arrangement Aug. 22, 1989
4743899 Decoder/multiplexer circuit including multi-emitter transistors May. 10, 1988
4682197 Power transistor with spaced subtransistors having individual collectors Jul. 21, 1987
4651409 Method of fabricating a high density, low power, merged vertical fuse/bipolar transistor Mar. 24, 1987
4571606 High density, high voltage power FET Feb. 18, 1986
4518874 Cascoded PLA array May. 21, 1985
4475119 Integrated circuit power transmission array Oct. 2, 1984
4373165 Very high density punch-through read-only-memory Feb. 8, 1983
4311926 Emitter coupled logic programmable logic arrays Jan. 19, 1982
3981072 Bipolar transistor construction method Sep. 21, 1976











 
 
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