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Class Information
Number: 257/E27.061
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Device consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate, e.g., integrated circuit device (epo) > Including semiconductor component with at least one potential barrier or surface barrier adapted for rectifying, oscillating, amplifying, or switching, or including integrated passive circuit elements (epo) > With semiconductor substrate only (epo) > Including only semiconductor components of a single kind, e.g., all bipolar transistors, all diodes, or all cmos (epo) > Including field-effect component only (epo) > Field-effect transistor with insulated gate (epo) > Combination of depletion and enhancement field-effect transistors (epo)
Description: This subclass is indented under subclass E27.06. This subclass is substantially the same in scope as ECLA classification H01L27/088D.










Patents under this class:
1 2 3

Patent Number Title Of Patent Date Issued
4183040 MOS RAM with implant forming peripheral depletion MOSFET channels and capacitor bottom electrodes Jan. 8, 1980
4178605 Complementary MOS inverter structure Dec. 11, 1979
4143286 Semiconductor memory device Mar. 6, 1979
4143390 Semiconductor device and a logical circuit formed of the same Mar. 6, 1979
4138782 Inverter with improved load line characteristic Feb. 13, 1979
4135102 High performance inverter circuits Jan. 16, 1979
4113515 Semiconductor manufacturing method using buried nitride formed by a nitridation treatment in the presence of active nitrogen Sep. 12, 1978
4107548 Ratioless type MIS logic circuit Aug. 15, 1978
4092548 Substrate bias modulation to improve mosfet circuit performance May. 30, 1978
4085498 Fabrication of integrated circuits containing enhancement-mode FETs and depletion-mode FETs with two layers of polycrystalline silicon utilizing five basic pattern delineating steps Apr. 25, 1978
4075045 Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capaci Feb. 21, 1978
4074301 Field inversion control for N-channel device integrated circuits Feb. 14, 1978
4072868 FET inverter with isolated substrate load Feb. 7, 1978
4069427 MIS logic circuit of ratioless type Jan. 17, 1978
4065783 Self-aligned double implanted short channel V-groove MOS device Dec. 27, 1977
4052229 Process for preparing a substrate for MOS devices of different thresholds Oct. 4, 1977
4034243 Logic array structure for depletion mode-FET load circuit technologies Jul. 5, 1977
4033026 High density/high speed MOS process and device Jul. 5, 1977
4015281 MIS-FETs isolated on common substrate Mar. 29, 1977
4011105 Field inversion control for N-channel device integrated circuits Mar. 8, 1977
4003071 Method of manufacturing an insulated gate field effect transistor Jan. 11, 1977
3995172 Enhancement-and depletion-type field effect transistors connected in parallel Nov. 30, 1976
3992639 Scanning device Nov. 16, 1976
3991326 MISFET switching circuit for a high withstand voltage Nov. 9, 1976
3983572 Semiconductor devices Sep. 28, 1976
3975718 Semiconductor arrangement, particularly a storage arrangement with field effect transistors, and method of operating the same Aug. 17, 1976
3952325 Semiconductor memory elements Apr. 20, 1976
RE28704 Semiconductor devices Feb. 3, 1976

1 2 3










 
 
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