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Class Information
Number: 257/E27.026
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Device consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate, e.g., integrated circuit device (epo) > Including semiconductor component with at least one potential barrier or surface barrier adapted for rectifying, oscillating, amplifying, or switching, or including integrated passive circuit elements (epo) > With semiconductor substrate only (epo) > Including a plurality of components in a non-repetitive configuration (epo) > Integrated circuit having a three-dimensional layout (epo)
Description: This subclass is indented under subclass E27.011. This subclass is substantially the same in scope as ECLA classification H01L27/06E.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 4698659 |
Stacked complementary metal oxide semiconductor inverter |
Oct. 6, 1987 |
| 4692994 |
Process for manufacturing semiconductor devices containing microbridges |
Sep. 15, 1987 |
| 4679299 |
Formation of self-aligned stacked CMOS structures by lift-off |
Jul. 14, 1987 |
| 4680609 |
Structure and fabrication of vertically integrated CMOS logic gates |
Jul. 14, 1987 |
| 4670768 |
Complementary MOS integrated circuits having vertical channel FETs |
Jun. 2, 1987 |
| 4670765 |
Semiconductor photodetector element |
Jun. 2, 1987 |
| 4669062 |
Two-tiered dynamic random access memory (DRAM) cell |
May. 26, 1987 |
| 4667217 |
Two bit vertically/horizontally integrated memory cell |
May. 19, 1987 |
| 4663648 |
Three dimensional structures of active and passive semiconductor components |
May. 5, 1987 |
| 4654121 |
Fabrication process for aligned and stacked CMOS devices |
Mar. 31, 1987 |
| 4654690 |
Capacitive elements with reduced stray capacitance |
Mar. 31, 1987 |
| 4649627 |
Method of fabricating silicon-on-insulator transistors with a shared element |
Mar. 17, 1987 |
| 4646266 |
Programmable semiconductor structures and methods for using the same |
Feb. 24, 1987 |
| 4641173 |
Integrated circuit load device |
Feb. 3, 1987 |
| 4639758 |
Metal oxide semiconductor field-effect transistor with metal source making ohmic contact to channel-base region |
Jan. 27, 1987 |
| 4635089 |
MIS-integrated semiconductor device |
Jan. 6, 1987 |
| 4633438 |
Stacked semiconductor memory |
Dec. 30, 1986 |
| 4631563 |
Metal oxide semiconductor field-effect transistor with metal source region |
Dec. 23, 1986 |
| 4630089 |
Semiconductor memory device |
Dec. 16, 1986 |
| 4622575 |
Integrated circuit bipolar memory cell |
Nov. 11, 1986 |
| 4620212 |
Semiconductor device with a resistor of polycrystalline silicon |
Oct. 28, 1986 |
| 4612563 |
High voltage integrated circuit |
Sep. 16, 1986 |
| 4609835 |
Semiconductor integrated circuit |
Sep. 2, 1986 |
| 4609407 |
Method of making three dimensional semiconductor devices in selectively laser regrown polysilicon or amorphous silicon layers |
Sep. 2, 1986 |
| 4603341 |
Stacked double dense read only memory |
Jul. 29, 1986 |
| 4593453 |
Two-level transistor structures and method utilizing minimal area therefor |
Jun. 10, 1986 |
| 4593300 |
Folded logic gate |
Jun. 3, 1986 |
| 4584594 |
Logic structure utilizing polycrystalline silicon Schottky diodes |
Apr. 22, 1986 |
| 4571609 |
Stacked MOS device with means to prevent substrate floating |
Feb. 18, 1986 |
| 4570175 |
Three-dimensional semiconductor device with thin film monocrystalline member contacting substrate at a plurality of locations |
Feb. 11, 1986 |
| 4569700 |
Method of manufacturing a stacked semiconductor device |
Feb. 11, 1986 |
| 4566025 |
CMOS Structure incorporating vertical IGFETS |
Jan. 21, 1986 |
| 4565712 |
Method of making a semiconductor read only memory |
Jan. 21, 1986 |
| 4555721 |
Structure of stacked, complementary MOS field effect transistor circuits |
Nov. 26, 1985 |
| 4554729 |
Method of making semiconductor memory device |
Nov. 26, 1985 |
| 4554570 |
Vertically integrated IGFET device |
Nov. 19, 1985 |
| 4554572 |
Self-aligned stacked CMOS |
Nov. 19, 1985 |
| 4544941 |
Semiconductor device having multiple conductive layers and the method of manufacturing the semiconductor device |
Oct. 1, 1985 |
| 4541006 |
Static memory having load polysilicon resistors formed over driver FET drains |
Sep. 10, 1985 |
| 4536785 |
One transistor dynamic random access memory |
Aug. 20, 1985 |
| 4533935 |
Semiconductor device and a method for manufacturing the same |
Aug. 6, 1985 |
| 4530149 |
Method for fabricating a self-aligned vertical IGFET |
Jul. 23, 1985 |
| 4529998 |
Amplified gate thyristor with non-latching amplified control transistors across base layers |
Jul. 16, 1985 |
| 4528582 |
Interconnection structure for polycrystalline silicon resistor and methods of making same |
Jul. 9, 1985 |
| 4504743 |
Semiconductor resistor element |
Mar. 12, 1985 |
| 4500905 |
Stacked semiconductor device with sloping sides |
Feb. 19, 1985 |
| 4498226 |
Method for manufacturing three-dimensional semiconductor device by sequential beam epitaxy |
Feb. 12, 1985 |
| 4494135 |
Programmable read only memory cell having an electrically destructible programmation element integrally formed with a junction diode |
Jan. 15, 1985 |
| 4492974 |
DMOS With gate protection diode formed over base region |
Jan. 8, 1985 |
| 4491742 |
Semiconductor switch device |
Jan. 1, 1985 |
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