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Class Information
Number: 257/E23.17
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Packaging, interconnects, and markings for semiconductor or other solid-state devices (epo) > Arrangements for conducting electric current within device in operation from one component to another, interconnections, e.g., wires, lead frames (epo) > Interconnection structure between plurality of semiconductor chips being formed on or in insulating substrates (epo) > Crossover interconnections, e.g., bridge stepovers (epo)
Description: This subclass is indented under subclass E23.169. This subclass is substantially the same in scope as ECLA classification H01L23/538A.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8604618 Structure and method for reducing vertical crack propagation Dec. 10, 2013
8592974 Package configurations for low EMI circuits Nov. 26, 2013
8487433 Semiconductor device Jul. 16, 2013
8455931 Package configurations for low EMI circuits Jun. 4, 2013
8426931 Semiconductor device and method of fabricating the semiconductor device Apr. 23, 2013
8344520 Stacked structure of chips Jan. 1, 2013
8304894 Super high-density module with integrated wafer level packages Nov. 6, 2012
8258014 Method of manufacturing a power transistor module and package with integrated bus bar Sep. 4, 2012
8207613 Semiconductor memory device Jun. 26, 2012
8178878 Mother thin film transistor array substrate and thin film transistor array substrate fabricated therefrom May. 15, 2012
8164753 Alignment mark arrangement and alignment mark structure Apr. 24, 2012
8138529 Package configurations for low EMI circuits Mar. 20, 2012
8129219 Semiconductor module, method for manufacturing the semiconductor module and portable device carrying the same Mar. 6, 2012
8115306 Apparatus and method for packaging circuits Feb. 14, 2012
8093700 Packaging millimeter wave modules Jan. 10, 2012
8053352 Method and mesh reference structures for implementing Z-axis cross-talk reduction through copper sputtering onto mesh reference planes Nov. 8, 2011
7994630 Power transistor package with integrated bus bar Aug. 9, 2011
7989932 Semiconductor device Aug. 2, 2011
7981771 Structures and methods to enhance Cu interconnect electromigration (EM) performance Jul. 19, 2011
7977232 Semiconductor wafer including cracking stopper structure and method of forming the same Jul. 12, 2011
7863615 Display unit and method of manufacturing the same Jan. 4, 2011
7846777 Semiconductor device package and fabricating method thereof Dec. 7, 2010
7800224 Power device package Sep. 21, 2010
7800184 Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact Sep. 21, 2010
7777338 Seal ring structure for integrated circuit chips Aug. 17, 2010
7745823 Thin film panel and method of manufacturing the same Jun. 29, 2010
7675169 Apparatus and method for packaging circuits Mar. 9, 2010
7663223 Coupling substrate for semiconductor components and method for producing the same Feb. 16, 2010
7629694 Interconnections for crosswire arrays Dec. 8, 2009
7626272 Via configurable architecture for customization of analog circuitry in a semiconductor device Dec. 1, 2009
7619307 Leadframe-based semiconductor package having arched bend in a supporting bar and leadframe for the package Nov. 17, 2009
7550854 Integrated interconnect arrangement Jun. 23, 2009
7544602 Method and structure for ultra narrow crack stop for multilevel semiconductor device Jun. 9, 2009
7444253 Air bridge structures and methods of making and using air bridge structures Oct. 28, 2008
7411304 Semiconductor interconnect having conductive spring contacts Aug. 12, 2008
7394155 Top and sidewall bridged interconnect structure and method Jul. 1, 2008
7391117 Method for fabricating semiconductor components with conductive spring contacts Jun. 24, 2008
7375421 High density multilayer circuit module May. 20, 2008
7112866 Method to form a cross network of air gaps within IMD layer Sep. 26, 2006
7102243 Mask-making member and its production method, mask and its making method, exposure process, and fabrication method of semiconductor device Sep. 5, 2006
6891387 System for probing, testing, burn-in, repairing and programming of integrated circuits May. 10, 2005
6838896 Method and system for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus Jan. 4, 2005
6798052 Fexible electronic device Sep. 28, 2004
6714625 Lithography device for semiconductor circuit pattern generation Mar. 30, 2004
6713327 Stress controlled dielectric integrated circuit fabrication Mar. 30, 2004
6682981 Stress controlled dielectric integrated circuit fabrication Jan. 27, 2004
6596624 Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a chip carrier Jul. 22, 2003
6294909 Electro-magnetic lithographic alignment method Sep. 25, 2001
6288561 Method and apparatus for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus Sep. 11, 2001
6268262 Method for forming air bridges Jul. 31, 2001

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