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Browse by Category: Main > Physics
Class Information
Number: 257/E23.167
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Packaging, interconnects, and markings for semiconductor or other solid-state devices (epo) > Arrangements for conducting electric current within device in operation from one component to another, interconnections, e.g., wires, lead frames (epo) > Including external interconnections consisting of multilayer structure of conductive and insulating layers inseparably formed on semiconductor body (epo) > Characterized by materials (epo) > Insulating materials (epo)
Description: This subclass is indented under subclass E23.154. This subclass is substantially the same in scope as ECLA classification H01L23/532N.










Patents under this class:

Patent Number Title Of Patent Date Issued
8633595 Semiconductor device having groove-shaped via-hole Jan. 21, 2014
8633594 Semiconductor device having groove-shaped via-hole Jan. 21, 2014
8617981 Semiconductor device and manufacturing method thereof Dec. 31, 2013
8592980 Carbon nanotube-modified low-K materials Nov. 26, 2013
8580697 CVD flowable gap fill Nov. 12, 2013
8471369 Method and apparatus for reducing plasma process induced damage in integrated circuits Jun. 25, 2013
8445995 Semiconductor structure with conductive plug in an oxide layer May. 21, 2013
8441127 Bump-on-trace structures with wide and narrow portions May. 14, 2013
8431480 Semiconductor device and manufacturing method thereof Apr. 30, 2013
8426970 Substrate processing including a masking layer Apr. 23, 2013
8410613 Semiconductor device having groove-shaped pattern Apr. 2, 2013
8405196 Chips having rear contacts connected by through vias to front contacts Mar. 26, 2013
8399301 Mounting structures for integrated circuit modules Mar. 19, 2013
8373282 Wafer level chip scale package with reduced stress on solder balls Feb. 12, 2013
8368204 Chip structure and process for forming the same Feb. 5, 2013
8362596 Engineered interconnect dielectric caps having compressive stress and interconnect structures containing same Jan. 29, 2013
8309402 Method of fabricating oxide material layer with openings attached to device layers Nov. 13, 2012
8258056 Method and material for forming a double exposure lithography pattern Sep. 4, 2012
8125013 Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors Feb. 28, 2012
8115318 Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method Feb. 14, 2012
8101990 Semiconductor device Jan. 24, 2012
8084294 Method of fabricating organic silicon film, semiconductor device including the same, and method of fabricating the semiconductor device Dec. 27, 2011
8080876 Structure and method for creating reliable deep via connections in a silicon carrier Dec. 20, 2011
8053893 Semiconductor device and manufacturing method thereof Nov. 8, 2011
8030779 Multi-layered metal interconnection Oct. 4, 2011
8026606 Interconnect layers without electromigration Sep. 27, 2011
8013423 Method for fabricating a metal interconnection using a dual damascene process and resulting semiconductor device Sep. 6, 2011
8008777 Method for manufacturing semiconductor device and the semiconductor device Aug. 30, 2011
8004083 Integrated circuit chips with fine-line metal and over-passivation metal Aug. 23, 2011
7977796 Semiconductor device and multilayer wiring board Jul. 12, 2011
7960838 Interconnect structure Jun. 14, 2011
7960821 Dummy vias for damascene process Jun. 14, 2011
7956462 Semiconductor device and manufacturing method thereof Jun. 7, 2011
7932609 Semiconductor device having groove-shaped via-hole Apr. 26, 2011
7928570 Interconnect structure Apr. 19, 2011
7906851 Semiconductor device having groove-shaped via-hole Mar. 15, 2011
7902683 Semiconductor arrangement and method for producing a semiconductor arrangement Mar. 8, 2011
7875549 Fluorine doped carbon films produced by modification by radicals Jan. 25, 2011
RE41948 Semiconductor device having multi-layered wiring Nov. 23, 2010
7825516 Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures Nov. 2, 2010
7796228 Display substrate, method of manufacturing the same and display device having the same Sep. 14, 2010
7795741 Semiconductor device Sep. 14, 2010
7791187 Semiconductor device Sep. 7, 2010
7777343 Semiconductor device and manufacturing method thereof Aug. 17, 2010
7768129 Metal etching method for an interconnect structure and metal interconnect structure obtained by such method Aug. 3, 2010
7767570 Dummy vias for damascene process Aug. 3, 2010
7759801 Tapered signal lines Jul. 20, 2010
7737561 Dual damascene integration of ultra low dielectric constant porous materials Jun. 15, 2010
7713862 Printed wiring board and method for manufacturing the same May. 11, 2010
7696086 Fabricating method of an interconnect structure Apr. 13, 2010











 
 
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