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Class Information
Number: 257/E23.167
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Packaging, interconnects, and markings for semiconductor or other solid-state devices (epo) > Arrangements for conducting electric current within device in operation from one component to another, interconnections, e.g., wires, lead frames (epo) > Including external interconnections consisting of multilayer structure of conductive and insulating layers inseparably formed on semiconductor body (epo) > Characterized by materials (epo) > Insulating materials (epo)
Description: This subclass is indented under subclass E23.154. This subclass is substantially the same in scope as ECLA classification H01L23/532N.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7608905 |
Independently addressable interdigitated nanowires |
Oct. 27, 2009 |
| 7598166 |
Dielectric layers for metal lines in semiconductor chips |
Oct. 6, 2009 |
| 7585758 |
Interconnect layers without electromigration |
Sep. 8, 2009 |
| 7579687 |
Circuit module turbulence enhancement systems and methods |
Aug. 25, 2009 |
| 7569477 |
Method for fabricating fine pattern in semiconductor device |
Aug. 4, 2009 |
| 7566658 |
Method for fabricating a metal interconnection using a dual damascene process and resulting semiconductor device |
Jul. 28, 2009 |
| 7566652 |
Electrically inactive via for electromigration reliability improvement |
Jul. 28, 2009 |
| 7563718 |
Method for forming tungsten layer of semiconductor device and method for forming tungsten wiring layer using the same |
Jul. 21, 2009 |
| 7563651 |
Method of fabricating a substrate with a concave surface |
Jul. 21, 2009 |
| 7557030 |
Method for fabricating a recess gate in a semiconductor device |
Jul. 7, 2009 |
| 7528491 |
Semiconductor components and assemblies including vias of varying lateral dimensions |
May. 5, 2009 |
| 7485963 |
Use of supercritical fluid for low effective dielectric constant metallization |
Feb. 3, 2009 |
| 7470611 |
In situ deposition of a low K dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
Dec. 30, 2008 |
| 7466027 |
Interconnect structures with surfaces roughness improving liner and methods for fabricating the same |
Dec. 16, 2008 |
| 7443032 |
Memory device with chemical vapor deposition of titanium for titanium silicide contacts |
Oct. 28, 2008 |
| 7414315 |
Damascene structure with high moisture-resistant oxide and method for making the same |
Aug. 19, 2008 |
| 7402883 |
Back end of the line structures with liner and noble metal layer |
Jul. 22, 2008 |
| 7368804 |
Method and apparatus of stress relief in semiconductor structures |
May. 6, 2008 |
| 7361991 |
Closed air gap interconnect structure |
Apr. 22, 2008 |
| 7338895 |
Method for dual damascene integration of ultra low dielectric constant porous materials |
Mar. 4, 2008 |
| 7335585 |
Method for preventing the formation of a void in a bottom anti-reflective coating filling a via hole |
Feb. 26, 2008 |
| 7301241 |
Semiconductor device for preventing defective filling of interconnection and cracking of insulating film |
Nov. 27, 2007 |
| 7291923 |
Tapered signal lines |
Nov. 6, 2007 |
| 7256146 |
Method of forming a ceramic diffusion barrier layer |
Aug. 14, 2007 |
| 7224064 |
Semiconductor device having conductive interconnections and porous and nonporous insulating portions |
May. 29, 2007 |
| 7208427 |
Precursor compositions and processes for MOCVD of barrier materials in semiconductor manufacturing |
Apr. 24, 2007 |
| 7180191 |
Semiconductor device and method of manufacturing a semiconductor device |
Feb. 20, 2007 |
| 7164191 |
Low relative permittivity SiO.sub.x film including a porous material for use with a semiconductor device |
Jan. 16, 2007 |
| 7157792 |
Forming a substantially planar upper surface at the outer edge of a semiconductor topography |
Jan. 2, 2007 |
| 7148535 |
Zero capacitance bondpad utilizing active negative capacitance |
Dec. 12, 2006 |
| 7115501 |
Method for fabricating an integrated circuit device with through-plating elements and terminal units |
Oct. 3, 2006 |
| 7105928 |
Copper wiring with high temperature superconductor (HTS) layer |
Sep. 12, 2006 |
| 7091618 |
Semiconductor device and method of manufacturing the same |
Aug. 15, 2006 |
| 7088003 |
Structures and methods for integration of ultralow-k dielectrics with improved reliability |
Aug. 8, 2006 |
| 7074717 |
Damascene processes for forming conductive structures |
Jul. 11, 2006 |
| 7071539 |
Chemical planarization performance for copper/low-k interconnect structures |
Jul. 4, 2006 |
| 7067426 |
Semiconductor processing methods |
Jun. 27, 2006 |
| 7067922 |
Semiconductor device |
Jun. 27, 2006 |
| 7064007 |
Method of using foamed insulators in three dimensional multichip structures |
Jun. 20, 2006 |
| 7064439 |
Integrated electrical circuit and method for fabricating it |
Jun. 20, 2006 |
| 7061081 |
Resin composition, heat-resistant resin paste and semiconductor device using them and method for manufacture thereof |
Jun. 13, 2006 |
| 7056822 |
Method of fabricating an interconnect structure employing air gaps between metal lines and between metal layers |
Jun. 6, 2006 |
| 7056839 |
Method of forming a silica insulation film with a reduced dielectric constant |
Jun. 6, 2006 |
| 7057287 |
Dual damascene integration of ultra low dielectric constant porous materials |
Jun. 6, 2006 |
| 7057289 |
Etch stop in damascene interconnect structure and method of making |
Jun. 6, 2006 |
| 7052932 |
Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication |
May. 30, 2006 |
| 7053487 |
Semiconductor device |
May. 30, 2006 |
| 7049249 |
Method of improving stability in low k barrier layers |
May. 23, 2006 |
| 7049686 |
Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
May. 23, 2006 |
| 7041586 |
Semiconductor device having a multilayer interconnection structure |
May. 9, 2006 |
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