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Class Information
Number: 257/E23.145
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Packaging, interconnects, and markings for semiconductor or other solid-state devices (epo) > Arrangements for conducting electric current within device in operation from one component to another, interconnections, e.g., wires, lead frames (epo) > Including external interconnections consisting of multilayer structure of conductive and insulating layers inseparably formed on semiconductor body (epo) > Via connections in multilevel interconnection structure (epo)
Description: This subclass is indented under subclass E23.142. This subclass is substantially the same in scope as ECLA classification H01L23/522E.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7618887 |
Semiconductor device with a metal line and method of forming the same |
Nov. 17, 2009 |
| 7612453 |
Semiconductor device having an interconnect structure and a reinforcing insulating film |
Nov. 3, 2009 |
| 7612451 |
Reducing resistivity in interconnect structures by forming an inter-layer |
Nov. 3, 2009 |
| 7605469 |
Atomic layer deposited tantalum containing adhesion layer |
Oct. 20, 2009 |
| 7605457 |
Semiconductor device and method of manufacturing the same |
Oct. 20, 2009 |
| 7605085 |
Method of manufacturing interconnecting structure with vias |
Oct. 20, 2009 |
| 7598616 |
Interconnect structure |
Oct. 6, 2009 |
| 7598615 |
Analytic structure for failure analysis of semiconductor device having a multi-stacked interconnection structure |
Oct. 6, 2009 |
| 7598614 |
Low leakage metal-containing cap process using oxidation |
Oct. 6, 2009 |
| 7595556 |
Semiconductor device and method for manufacturing the same |
Sep. 29, 2009 |
| 7595529 |
Semiconductor integrated circuit devices having upper pattern aligned with lower pattern molded by semiconductor substrate and methods of forming the same |
Sep. 29, 2009 |
| 7586175 |
Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surface |
Sep. 8, 2009 |
| 7585760 |
Method for forming planarizing copper in a low-k dielectric |
Sep. 8, 2009 |
| 7576433 |
Semiconductor memory device and manufacturing method thereof |
Aug. 18, 2009 |
| 7576002 |
Multi-step barrier deposition method |
Aug. 18, 2009 |
| 7572723 |
Micropad for bonding and a method therefor |
Aug. 11, 2009 |
| 7566974 |
Doped polysilicon via connecting polysilicon layers |
Jul. 28, 2009 |
| 7566652 |
Electrically inactive via for electromigration reliability improvement |
Jul. 28, 2009 |
| 7564135 |
Semiconductor device having self-aligned contact and method of fabricating the same |
Jul. 21, 2009 |
| 7563718 |
Method for forming tungsten layer of semiconductor device and method for forming tungsten wiring layer using the same |
Jul. 21, 2009 |
| 7560814 |
Semiconductor device that improves electrical connection reliability |
Jul. 14, 2009 |
| 7560378 |
Method for manufacturing semiconductor device |
Jul. 14, 2009 |
| 7557449 |
Flexible via design to improve reliability |
Jul. 7, 2009 |
| 7553703 |
Methods of forming an interconnect structure |
Jun. 30, 2009 |
| 7550828 |
Leadframe package for MEMS microphone assembly |
Jun. 23, 2009 |
| 7550822 |
Dual-damascene metal wiring patterns for integrated circuit devices |
Jun. 23, 2009 |
| 7550321 |
Substrate having a functionally gradient coefficient of thermal expansion |
Jun. 23, 2009 |
| 7547935 |
Semiconductor devices including buried digit lines that are laterally offset from corresponding active-device regions |
Jun. 16, 2009 |
| 7538434 |
Copper interconnection with conductive polymer layer and method of forming the same |
May. 26, 2009 |
| 7525196 |
Protection of seedlayer for electroplating |
Apr. 28, 2009 |
| 7524753 |
Semiconductor device having through electrode and method of manufacturing the same |
Apr. 28, 2009 |
| 7518247 |
Semiconductor device and its manufacturing method |
Apr. 14, 2009 |
| 7518192 |
Asymmetrical layout structure for ESD protection |
Apr. 14, 2009 |
| 7514792 |
Semiconductor device and manufacturing method thereof |
Apr. 7, 2009 |
| 7511780 |
Active matrix liquid crystal display device |
Mar. 31, 2009 |
| 7511378 |
Enhancement of performance of a conductive wire in a multilayered substrate |
Mar. 31, 2009 |
| 7507656 |
Method and structure for low k interlayer dielectric layer |
Mar. 24, 2009 |
| 7504731 |
Interconnect structure to reduce stress induced voiding effect |
Mar. 17, 2009 |
| 7504730 |
Memory elements |
Mar. 17, 2009 |
| 7504724 |
Semiconductor device |
Mar. 17, 2009 |
| 7504333 |
Method of forming bit line of semiconductor device |
Mar. 17, 2009 |
| 7498659 |
Semiconductor device, method of manufacturing the same, and phase shift mask |
Mar. 3, 2009 |
| 7485963 |
Use of supercritical fluid for low effective dielectric constant metallization |
Feb. 3, 2009 |
| 7482694 |
Semiconductor device and its manufacturing method |
Jan. 27, 2009 |
| 7482264 |
Method of forming metal line of semiconductor device, and semiconductor device |
Jan. 27, 2009 |
| 7473984 |
Method for fabricating a metal-insulator-metal capacitor |
Jan. 6, 2009 |
| 7473597 |
Method of forming via structures and method of fabricating phase change memory devices incorporating such via structures |
Jan. 6, 2009 |
| 7470988 |
Chip structure and process for forming the same |
Dec. 30, 2008 |
| 7470616 |
Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention |
Dec. 30, 2008 |
| 7466027 |
Interconnect structures with surfaces roughness improving liner and methods for fabricating the same |
Dec. 16, 2008 |
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