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Class Information
Number: 257/E23.141
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Packaging, interconnects, and markings for semiconductor or other solid-state devices (epo) > Arrangements for conducting electric current within device in operation from one component to another, interconnections, e.g., wires, lead frames (epo)
Description: This subclass is indented under subclass E23.001. This subclass is substantially the same in scope as ECLA classification H01L23/52.










Sub-classes under this class:

Class Number Class Name Patents
257/E23.142 Including external interconnections consisting of multilayer structure of conductive and insulating layers inseparably formed on semiconductor body (epo) 514
257/E23.168 Including internal interconnections, e.g., cross-under constructions (epo) 203
257/E23.169 Interconnection structure between plurality of semiconductor chips being formed on or in insulating substrates (epo) 429


Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12

Patent Number Title Of Patent Date Issued
8710660 Hybrid interconnect scheme including aluminum metal line in low-k dielectric Apr. 29, 2014
8710655 Die packages and systems having the die packages Apr. 29, 2014
8704353 Thermal management of stacked semiconductor chips with electrically non-functional interconnects Apr. 22, 2014
8692382 Chip package Apr. 8, 2014
8686565 Stacked chip assembly having vertical vias Apr. 1, 2014
8686536 Electrical fuse structure and method of formation Apr. 1, 2014
8686570 Multi-dimensional integrated circuit structures and methods of forming the same Apr. 1, 2014
8686572 Apparatus for stacking integrated circuits Apr. 1, 2014
8680680 Semiconductor devices including porous insulators Mar. 25, 2014
8674520 Semiconductor device, method for manufacturing the same, and power supply unit Mar. 18, 2014
8664774 Bondwire configuration for reduced crosstalk Mar. 4, 2014
8659169 Corner structure for IC die Feb. 25, 2014
8659175 Integrated circuit package system with offset stack Feb. 25, 2014
8653639 Layered chip package and method of manufacturing same Feb. 18, 2014
8653663 Barrier layer for copper interconnect Feb. 18, 2014
8653674 Electronic component package fabrication method and structure Feb. 18, 2014
8648453 Semiconductor device and method for manufacturing the same Feb. 11, 2014
8643083 Electronic devices with ultraviolet blocking layers Feb. 4, 2014
8637989 Semiconductor chip having via electrodes and stacked semiconductor chips interconnected by the via electrodes Jan. 28, 2014
8624398 Semiconductor circuit structure Jan. 7, 2014
8624242 Semiconductor integrated circuit Jan. 7, 2014
8618821 Device for detecting the thinning down of the substrate of an integrated circuit chip Dec. 31, 2013
8619003 Semiconductor device with wireless communication Dec. 31, 2013
8614515 Wiring method for semiconductor integrated circuit, semiconductor-circuit wiring apparatus and semiconductor integrated circuit Dec. 24, 2013
8610276 Metal cap for back end of line (BEOL) interconnects, design structure and method of manufacture Dec. 17, 2013
8610279 Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods Dec. 17, 2013
8610288 Semiconductor device with stacked semiconductor chips Dec. 17, 2013
8604557 Semiconductor memory device and method for manufacturing Dec. 10, 2013
8598718 Three-dimensional multichip module Dec. 3, 2013
8598695 Active chip on carrier or laminated chip having microelectronic element embedded therein Dec. 3, 2013
8598677 Semiconductor device including metal lines Dec. 3, 2013
8592259 Method of fabricating a wafer level semiconductor package having a pre-formed dielectric layer Nov. 26, 2013
8592969 Semiconductor device with protective screen Nov. 26, 2013
8587123 Multi-chip and multi-substrate reconstitution based packaging Nov. 19, 2013
8587088 Side-mounted controller and methods for making the same Nov. 19, 2013
8586422 Optical semiconductor device having pre-molded leadframe with window and method therefor Nov. 19, 2013
8580607 Microelectronic packages with nanoparticle joining Nov. 12, 2013
8580682 Cost-effective TSV formation Nov. 12, 2013
8580688 Copper interconnection structure and method for forming copper interconnections Nov. 12, 2013
8575021 Substrate processing including a masking layer Nov. 5, 2013
8576000 3D chip stack skew reduction with resonant clock and inductive coupling Nov. 5, 2013
8569878 Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same Oct. 29, 2013
8569887 Post passivation interconnect with oxidation prevention layer Oct. 29, 2013
8563419 Method of manufacturing an interconnect structure and design structure thereof Oct. 22, 2013
8563427 Semiconductor chip with conductive diffusion regions, method for manufacturing the same, and stack package using the same Oct. 22, 2013
8564077 Package for electronic component, manufacturing method thereof and sensing apparatus Oct. 22, 2013
8564134 Semiconductor substrate, semiconductor device, and manufacturing methods thereof Oct. 22, 2013
8558277 Semiconductor device and method of providing electrostatic discharge protection for integrated passive devices Oct. 15, 2013
8551814 Method of fabricating a semiconductor device that limits damage to elements of the semiconductor device that are exposed during processing Oct. 8, 2013
8552561 Semiconductor device with output circuit arrangement Oct. 8, 2013

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