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Class Information
Number: 257/E23.019
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Packaging, interconnects, and markings for semiconductor or other solid-state devices (epo) > Arrangements for conducting electric current to or from solid-state body in operation, e.g., leads, terminal arrangements (epo) > Consisting of lead-in layers inseparably applied to semiconductor body (epo) > Consisting of layered constructions comprising conductive layers and insulating layers, e.g., planar contacts (epo)
Description: This subclass is indented under subclass E23.012. This subclass is substantially the same in scope as ECLA classification H01L23/485.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7598615 |
Analytic structure for failure analysis of semiconductor device having a multi-stacked interconnection structure |
Oct. 6, 2009 |
| 7592244 |
Semiconductor device and method of manufacturing the same |
Sep. 22, 2009 |
| RE40887 |
Semiconductor chip with redistribution metal layer |
Sep. 1, 2009 |
| 7582909 |
Mounting and adhesive layer for semiconductor components |
Sep. 1, 2009 |
| 7576424 |
Semiconductor device |
Aug. 18, 2009 |
| 7569877 |
System and method based on field-effect transistors for addressing nanometer-scale devices |
Aug. 4, 2009 |
| 7566972 |
Semiconductor device and method for manufacturing the semiconductor device |
Jul. 28, 2009 |
| 7557436 |
Semiconductor device and IC card including supply voltage wiring lines formed in different areas and having different shapes |
Jul. 7, 2009 |
| 7554176 |
Integrated circuits having a multi-layer structure with a seal ring |
Jun. 30, 2009 |
| 7553762 |
Method for forming metal silicide layer |
Jun. 30, 2009 |
| 7550849 |
Conductive structures including titanium-tungsten base layers |
Jun. 23, 2009 |
| 7545046 |
Semiconductor devices having a trench in a side portion of a conducting line pattern and methods of forming the same |
Jun. 9, 2009 |
| 7535095 |
Printed wiring board and method for producing the same |
May. 19, 2009 |
| 7528069 |
Fine pitch interconnect and method of making |
May. 5, 2009 |
| 7524697 |
Method for manufactuing a semiconductor integrated circuit device |
Apr. 28, 2009 |
| 7514276 |
Aligning stacked chips using resistance assistance |
Apr. 7, 2009 |
| 7508082 |
Semiconductor device and method of manufacturing the same |
Mar. 24, 2009 |
| 7504719 |
Printed wiring board having a roughened surface formed on a metal layer, and method for producing the same |
Mar. 17, 2009 |
| 7485560 |
Method for fabricating crystalline silicon thin films |
Feb. 3, 2009 |
| 7459781 |
Fan out type wafer level package structure and method of the same |
Dec. 2, 2008 |
| 7459795 |
Method to build a wirebond probe card in a many at a time fashion |
Dec. 2, 2008 |
| 7449772 |
Chip-type electronic component including thin-film circuit elements |
Nov. 11, 2008 |
| 7414309 |
Encapsulated electronic part packaging structure |
Aug. 19, 2008 |
| 7397103 |
Semiconductor with damage detection circuitry |
Jul. 8, 2008 |
| 7375421 |
High density multilayer circuit module |
May. 20, 2008 |
| 7351656 |
Semiconductor device having oxidized metal film and manufacture method of the same |
Apr. 1, 2008 |
| 7335964 |
Semiconductor structures |
Feb. 26, 2008 |
| 7332799 |
Packaged chip having features for improved signal transmission on the package |
Feb. 19, 2008 |
| 7327031 |
Semiconductor device and method of manufacturing the same |
Feb. 5, 2008 |
| 7291875 |
Semiconductor device with double barrier film |
Nov. 6, 2007 |
| 7285842 |
Siloxane epoxy polymers as metal diffusion barriers to reduce electromigration |
Oct. 23, 2007 |
| 7285858 |
Semiconductor device and its manufacture method capable of preventing short circuit of electrodes when semiconductor device is mounted on sub-mount substrate |
Oct. 23, 2007 |
| 7268433 |
Semiconductor device |
Sep. 11, 2007 |
| 7265437 |
Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties |
Sep. 4, 2007 |
| 7247947 |
Semiconductor device comprising a plurality of semiconductor constructs |
Jul. 24, 2007 |
| 7215027 |
Electrical coupling stack and processes for making same |
May. 8, 2007 |
| 7193324 |
Circuit structure of package substrate |
Mar. 20, 2007 |
| 7193314 |
Semiconductor devices and substrates used in thereof |
Mar. 20, 2007 |
| 7180168 |
Stacked semiconductor chips |
Feb. 20, 2007 |
| 7173330 |
Multiple chip semiconductor package |
Feb. 6, 2007 |
| 7078812 |
Routing differential signal lines in a substrate |
Jul. 18, 2006 |
| 7071563 |
Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer |
Jul. 4, 2006 |
| 7067920 |
Semiconductor device and method of fabricating the same |
Jun. 27, 2006 |
| 7067416 |
Method of forming a conductive contact |
Jun. 27, 2006 |
| 7064051 |
Method of forming self-aligned contact pads of non-straight type semiconductor memory device |
Jun. 20, 2006 |
| 7060543 |
Method of forming a conductive line for a semiconductor device using a carbon nanotube and semiconductor device manufactured using the method |
Jun. 13, 2006 |
| 7060555 |
Semiconductor device and method of manufacturing the same |
Jun. 13, 2006 |
| 7049702 |
Damascene structure at semiconductor substrate level |
May. 23, 2006 |
| 7041605 |
Semiconductor contact structure and method of forming the same |
May. 9, 2006 |
| 7041594 |
Semiconductor device for applying well bias and method of fabricating the same |
May. 9, 2006 |
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