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Class Information
Number: 257/E23.011
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Packaging, interconnects, and markings for semiconductor or other solid-state devices (epo) > Arrangements for conducting electric current to or from solid-state body in operation, e.g., leads, terminal arrangements (epo) > Internal lead connections, e.g., via connections, feedthrough structures (epo)
Description: This subclass is indented under subclass E23.01. This subclass is substantially the same in scope as ECLA classification H01L23/48J.










Patents under this class:

Patent Number Title Of Patent Date Issued
8710670 Integrated circuit packaging system with coupling features and method of manufacture thereof Apr. 29, 2014
8710668 Integrated circuit packaging system with laser hole and method of manufacture thereof Apr. 29, 2014
8710658 Under bump passive components in wafer level packaging Apr. 29, 2014
8710655 Die packages and systems having the die packages Apr. 29, 2014
8710647 Semiconductor device having a first conductive member connecting a chip to a wiring board pad and a second conductive member connecting the wiring board pad to a land on an insulator covering Apr. 29, 2014
8709945 Area efficient through-hole connections Apr. 29, 2014
8709938 3D IC method and device Apr. 29, 2014
8709865 Fabrication method of packaging substrate having through-holed interposer embedded therein Apr. 29, 2014
8704364 Reducing stress in multi-die integrated circuit structures Apr. 22, 2014
8704358 Method for forming an integrated circuit Apr. 22, 2014
8704356 High temperature interconnect assemblies for high temperature electronics utilizing transition pads Apr. 22, 2014
8704339 Semiconductor device Apr. 22, 2014
8703542 Wafer-level packaging mechanisms Apr. 22, 2014
8692383 Semiconductor device and method of manufacturing the same Apr. 8, 2014
8692382 Chip package Apr. 8, 2014
8692371 Semiconductor apparatus and manufacturing method thereof Apr. 8, 2014
8686567 Semiconductor device having plural wiring layers Apr. 1, 2014
8686565 Stacked chip assembly having vertical vias Apr. 1, 2014
8685796 Electronic device and method of manufacturing the same Apr. 1, 2014
8674514 Wiring board, manufacturing method of the wiring board, and semiconductor package Mar. 18, 2014
8674510 Three-dimensional integrated circuit structure having improved power and thermal management Mar. 18, 2014
8673769 Methods and apparatuses for three dimensional integrated circuits Mar. 18, 2014
8669655 Chip package and a method for manufacturing a chip package Mar. 11, 2014
8669142 Method of manufacturing package structure Mar. 11, 2014
8664772 Interface substrate with interposer Mar. 4, 2014
8664768 Interposer having a defined through via pattern Mar. 4, 2014
8664767 Conductive routings in integrated circuits using under bump metallization Mar. 4, 2014
8664761 Semiconductor structure and manufacturing method of the same Mar. 4, 2014
8659120 Semiconductor device substrate and semiconductor device Feb. 25, 2014
8659096 Semiconductor device Feb. 25, 2014
8659019 Semiconductor device Feb. 25, 2014
8658485 Semiconductor device and method of fabricating the same Feb. 25, 2014
8653670 Electrical interconnect for an integrated circuit package and method of making same Feb. 18, 2014
8653663 Barrier layer for copper interconnect Feb. 18, 2014
8653648 Zigzag pattern for TSV copper adhesion Feb. 18, 2014
8653645 Semiconductor device comprising stacked LSI having circuit blocks connected by power supply and signal line through vias Feb. 18, 2014
8653644 Packaged semiconductor chips with array Feb. 18, 2014
8648454 Wafer-scale package structures with integrated antennas Feb. 11, 2014
8647979 Buffer layer to enhance photo and/or laser sintering Feb. 11, 2014
8643149 Stress barrier structures for semiconductor chips Feb. 4, 2014
8643083 Electronic devices with ultraviolet blocking layers Feb. 4, 2014
8642444 Method of manufacturing bonded substrate, bonded substrate, method of manufacturing solid-state imaging apparatus, solid-state imaging apparatus, and camera Feb. 4, 2014
8637996 Perforation patterned electrical interconnects Jan. 28, 2014
8637991 Microelectronic package with terminals on dielectric mass Jan. 28, 2014
8637990 Semiconductor device and method for fabricating the same Jan. 28, 2014
8633107 Method of producing a semiconductor device and semiconductor device having a through-wafer interconnect Jan. 21, 2014
8629562 Techniques for modular chip fabrication Jan. 14, 2014
8629559 Stress reduction apparatus with an inverted cup-shaped layer Jan. 14, 2014
8629546 Stacked redistribution layer (RDL) die assembly package Jan. 14, 2014
8629499 Vertical MOSFET device Jan. 14, 2014











 
 
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