Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Browse by Category: Main > Physics
Class Information
Number: 257/E21.702
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > Substrate is nonsemiconductor body, e.g., insulating body (epo) > To produce devices, each consisting of single circuit element (epo)
Description: This subclass is indented under subclass E21.599. This subclass is substantially the same in scope as ECLA classification H01L21/786.










Patents under this class:

Patent Number Title Of Patent Date Issued
8598664 Field effect transistor (FET) and method of forming the FET without damaging the wafer surface Dec. 3, 2013
8535996 Substrate having a charged zone in an insulating buried layer Sep. 17, 2013
8420467 Semiconductor device and method for manufacturing the same Apr. 16, 2013
8334172 Manufacturing method of semiconductor device Dec. 18, 2012
8237153 Forming a non-planar transistor having a quantum well channel Aug. 7, 2012
8106498 Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof Jan. 31, 2012
7928426 Forming a non-planar transistor having a quantum well channel Apr. 19, 2011
7811859 Method of reducing memory card edge roughness by edge coating Oct. 12, 2010
7696009 Method for fabricating a semiconductor device having a heat radiation layer Apr. 13, 2010
7582512 Method of fabricating semiconductor device having conducting portion of upper and lower conductive layers on a peripheral surface of the semiconductor device Sep. 1, 2009
6613650 Active matrix ESD protection and testing scheme Sep. 2, 2003











 
 
  Recently Added Patents
Rechargeable battery including a channel member
Expressive grouping for language integrated queries
Medical imaging probe with rotary encoder
System and method for providing definitions
Event-triggered server-side macros
6-O-substituted benzoxazole and benzothiazole compounds and methods of inhibiting CSF-1R signaling
Light emitted diode
  Randomly Featured Patents
Semiconductor wafer assemblies comprising photoresist over silicon nitride materials
Clear case for an inflation kit
System and method for a redundant communication channel via storage area network back-end
Stackable and nestable receptacles
Nanoprobe tip for advanced scanning probe microscopy comprising a layered probe material patterned by lithography and/or FIB techniques
Composition and method for corrosion protection of a structure
Work supporting members for glue applying machines
Light quantity control apparatus
Concealed crash wall in combination with mechanically stabilized earth construction
Leakage resistance carton