Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Browse by Category: Main > Physics
Class Information
Number: 257/E21.702
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > Substrate is nonsemiconductor body, e.g., insulating body (epo) > To produce devices, each consisting of single circuit element (epo)
Description: This subclass is indented under subclass E21.599. This subclass is substantially the same in scope as ECLA classification H01L21/786.










Patents under this class:

Patent Number Title Of Patent Date Issued
8598664 Field effect transistor (FET) and method of forming the FET without damaging the wafer surface Dec. 3, 2013
8535996 Substrate having a charged zone in an insulating buried layer Sep. 17, 2013
8420467 Semiconductor device and method for manufacturing the same Apr. 16, 2013
8334172 Manufacturing method of semiconductor device Dec. 18, 2012
8237153 Forming a non-planar transistor having a quantum well channel Aug. 7, 2012
8106498 Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof Jan. 31, 2012
7928426 Forming a non-planar transistor having a quantum well channel Apr. 19, 2011
7811859 Method of reducing memory card edge roughness by edge coating Oct. 12, 2010
7696009 Method for fabricating a semiconductor device having a heat radiation layer Apr. 13, 2010
7582512 Method of fabricating semiconductor device having conducting portion of upper and lower conductive layers on a peripheral surface of the semiconductor device Sep. 1, 2009
6613650 Active matrix ESD protection and testing scheme Sep. 2, 2003











 
 
  Recently Added Patents
Method and system for providing status of a machine
Ottoman
Monitoring heap in real-time by a mobile agent to assess performance of virtual machine
Using location based services for determining a calling window
Soybean cultivar CL0911444
Method and apparatus for variable accuracy inter-picture timing specification for digital video encoding
Knife grip
  Randomly Featured Patents
Absorbable dusting powder derived from starch
Integrated silicon bridge detonator
Integrated thermoelectric cooling devices and methods for fabricating same
Light fixture
Electric machine having a liquid-cooled rotor
Method and apparatus for the time synchronization in a data communication system
Transformable toy
Structure of hybrid vehicle
Card issuing apparatus having sequential processing units
Multiple axes external bone fixing member