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Class Information
Number: 257/E21.699
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate is semiconductor other than diamond, sic, si, group iii-v compound, or group ii-vi compound (epo)
Description: This subclass is indented under subclass E21.602. This subclass is substantially the same in scope as ECLA classification H01L21/8256.










Patents under this class:

Patent Number Title Of Patent Date Issued
8105885 Hardened programmable devices Jan. 31, 2012
8058174 Method for treating semiconductor processing components and components formed thereby Nov. 15, 2011
7811943 Process for producing silicon carbide crystals having increased minority carrier lifetimes Oct. 12, 2010
7666795 Method for manufacturing semiconductor device Feb. 23, 2010
7378334 Nitride semiconductor device comprising bonded substrate and fabrication method of the same May. 27, 2008
7368763 Semiconductor device and manufacturing method thereof May. 6, 2008
7226805 Sequential lithographic methods to reduce stacking fault nucleation sites Jun. 5, 2007
7109521 Silicon carbide semiconductor structures including multiple epitaxial layers having sidewalls Sep. 19, 2006
6984554 Transistor with group III/VI emitter Jan. 10, 2006
6903386 Transistor with means for providing a non-silicon-based emitter Jun. 7, 2005
6111267 CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon lay Aug. 29, 2000
5998807 Integrated CMOS circuit arrangement and method for the manufacture thereof Dec. 7, 1999
5840596 Method of manufacturing complementary modulation-doped field effect transistors Nov. 24, 1998
5798555 Enhancement-depletion logic based on Ge mosfets Aug. 25, 1998
5650337 Monolithic optoelectronic and electronic structures Jul. 22, 1997
5534713 Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers Jul. 9, 1996
5447882 Method for fabricating capacitor of semiconductor memory device Sep. 5, 1995











 
 
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