Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Read-only memory structures (rom), i.e., nonvolatile memory structures (epo) > Electrically programmable (eprom), i.e., floating gate memory structures (epo) > With conductive layer as control gate (epo) > With source and drain on same level and without cell select transistor (epo) > Simultaneous fabrication of periphery and memory cells (epo) > Including different types of peripheral fets (epo) > Patents

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Class Information
Number: 257/E21.689
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Read-only memory structures (rom), i.e., nonvolatile memory structures (epo) > Electrically programmable (eprom), i.e., floating gate memory structures (epo) > With conductive layer as control gate (epo) > With source and drain on same level and without cell select transistor (epo) > Simultaneous fabrication of periphery and memory cells (epo) > Including different types of peripheral fets (epo)
Description: This subclass is indented under subclass E21.683. This subclass is substantially the same in scope as ECLA classification H01L21/8247M2P2.

Patents under this class:

1 2 3 4 5 6 7 8

Patent Number	Title Of Patent	Date Issued
6197639	Method for manufacturing NOR-type flash memory device	Mar. 6, 2001
6194320	Method for preparing a semiconductor device	Feb. 27, 2001
6194270	Process for the manufacturing of an electrically programmable non-volatile memory device	Feb. 27, 2001
6184093	Method of implementing differential gate oxide thickness for flash EEPROM	Feb. 6, 2001
6180996	Semiconductor device comprising a polydiode element	Jan. 30, 2001
6180456	Triple polysilicon embedded NVRAM cell and method thereof	Jan. 30, 2001
6181598	Data line disturbance free memory block divided flash memory and microcomputer having flash memory	Jan. 30, 2001
6177362	Fabrication method for gate structure having gate dielectric layers of different thickness	Jan. 23, 2001
6174759	Method of manufacturing a semiconductor device	Jan. 16, 2001
6166953	Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein	Dec. 26, 2000
6166958	Semiconductor memory device, method for manufacturing the same, and method for controlling the same	Dec. 26, 2000
6166419	Semiconductor memory device	Dec. 26, 2000
6165846	Method of eliminating gate leakage in nitrogen annealed oxides	Dec. 26, 2000
6162683	System and method for forming an inter-layer dielectric in floating gate memory devices	Dec. 19, 2000
6159795	Low voltage junction and high voltage junction optimization for flash memory	Dec. 12, 2000
6159799	Method of manufacturing semiconductor device comprising high voltage regions and floating gates	Dec. 12, 2000
6156609	EEPROM device manufacturing method	Dec. 5, 2000
6133093	Method for forming an integrated circuit	Oct. 17, 2000
6130836	Semiconductor IC device having a control register for designating memory blocks for erasure	Oct. 10, 2000
6130168	Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process	Oct. 10, 2000
6127696	High voltage MOS transistor for flash EEPROM applications having a uni-sided lightly doped drain	Oct. 3, 2000
6125060	Flash EEPROM device employing polysilicon sidewall spacer as an erase gate	Sep. 26, 2000
6124157	Integrated non-volatile and random access memory and method of forming the same	Sep. 26, 2000
6121087	Integrated circuit device with embedded flash memory and method for manufacturing same	Sep. 19, 2000
6117730	Integrated method by using high temperature oxide for top oxide and periphery gate oxide	Sep. 12, 2000
6114767	EEPROM semiconductor device and method of fabricating the same	Sep. 5, 2000
6104059	Non-volatile memory having a silicide film on memory control gates and peripheral circuit transistor gates	Aug. 15, 2000
6087211	Method for forming a semiconductor device having non-volatile memory cells, High-voltage transistors, and low-voltage, deep sub-micron transistors	Jul. 11, 2000
6069033	Method of manufacturing a non-volatile memory and a CMOS transistor	May. 30, 2000
6069389	Semiconductor non-volatile memory device having floating gate type field effect transistors for memory cells bipolar transistors for a high-speed circuit	May. 30, 2000
6064606	Semiconductor integrated circuit device	May. 16, 2000
6064593	Semiconductor integrated circuit device having an electrically erasable and programmable nonvolatile memory and a built-in processing unit	May. 16, 2000
6043530	Flash EEPROM device employing polysilicon sidewall spacer as an erase gate	Mar. 28, 2000
6043123	Triple well flash memory fabrication process	Mar. 28, 2000
6037625	Semiconductor device with salicide structure and fabrication method thereof	Mar. 14, 2000
6026020	Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein	Feb. 15, 2000
6022778	Process for the manufacturing of integrated circuits comprising low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells	Feb. 8, 2000
6023085	Core cell structure and corresponding process for NAND-type high performance flash memory device	Feb. 8, 2000
6020610	Semiconductor device and method of manufacturing the same	Feb. 1, 2000
6010946	Semiconductor device with isolation insulating film tapered and method of manufacturing the same	Jan. 4, 2000
6004847	Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC	Dec. 21, 1999
5998828	Semiconductor device having nitrogen introduced in its polysilicon gate	Dec. 7, 1999
5994733	Nonvolatile semiconductor memory device and method of fabricating the same	Nov. 30, 1999
5991204	Flash eeprom device employing polysilicon sidewall spacer as an erase gate	Nov. 23, 1999
5977586	Non-volatile integrated low-doped drain device with partially overlapping gate regions	Nov. 2, 1999
5969382	EPROM in high density CMOS having added substrate diffusion	Oct. 19, 1999
5962888	Well structure non-volatile memory device and method for fabricating the same	Oct. 5, 1999
5960274	Oxide formation process for manufacturing programmable logic device	Sep. 28, 1999
5946230	Nonvolatile semiconductor memory device having the reliability of gate insulating film of memory cells enhanced and method for manufacturing the same	Aug. 31, 1999
5932920	Nonvolatile memory device and manufacturing method thereof	Aug. 3, 1999