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Class Information
Number: 257/E21.684
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Read-only memory structures (rom), i.e., nonvolatile memory structures (epo) > Electrically programmable (eprom), i.e., floating gate memory structures (epo) > With conductive layer as control gate (epo) > With source and drain on same level and without cell select transistor (epo) > Simultaneous fabrication of periphery and memory cells (epo) > Including one type of peripheral fet (epo)
Description: This subclass is indented under subclass E21.683. This subclass is substantially the same in scope as ECLA classification H01L21/8247M2P1.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.685 Control gate layer used for peripheral fet (epo) 100
257/E21.686 Intergate dielectric layer used for peripheral fet (epo) 40
257/E21.687 Floating gate layer used for peripheral fet (epo) 57
257/E21.688 Floating gate dielectric layer used for peripheral fet (epo) 164


Patents under this class:
1 2

Patent Number Title Of Patent Date Issued
8048757 Method for fabricating capacitor utilizes a sacrificial pattern enclosing the upper outer walls of the storage nodes Nov. 1, 2011
7869279 EEPROM memory device and method of programming memory cell having N erase pocket and program and access transistors Jan. 11, 2011
7560342 Method of manufacturing a semiconductor device having a plurality of memory and non-memory devices Jul. 14, 2009
7491657 Method of manufacturing a semiconductor device having a one time programmable (OTP) erasable and programmable read only memory (EPROM) cell Feb. 17, 2009
7468302 Method of forming trench type isolation film of semiconductor device Dec. 23, 2008
7465630 Method for manufacturing flash memory device Dec. 16, 2008
7462904 Non-volatile memory devices and methods of forming the same Dec. 9, 2008
7166510 Method for manufacturing flash memory device Jan. 23, 2007
7091091 Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer Aug. 15, 2006
7061044 Non-volatile memory device Jun. 13, 2006
7060565 Fabrication of dielectric for a nonvolatile memory cell having multiple floating gates Jun. 13, 2006
7045418 Semiconductor device including a dielectric layer having a gettering material located therein and a method of manufacture therefor May. 16, 2006
7023047 MOS device and process for manufacturing MOS devices using dual-polysilicon layer technology Apr. 4, 2006
7018890 Non-volatile semiconductor memory device and manufacturing method thereof Mar. 28, 2006
6949790 Semiconductor device and its manufacturing method Sep. 27, 2005
6949803 Manufacturing process for a high voltage transistor integrated on a semiconductor substrate with non-volatile memory cells and corresponding transistor Sep. 27, 2005
6927129 Narrow wide spacer Aug. 9, 2005
6872667 Method of fabricating semiconductor device with separate periphery and cell region etching steps Mar. 29, 2005
6846716 Integrated circuit device and method therefor Jan. 25, 2005
6828183 Process for high voltage oxide and select gate poly for split-gate flash memory Dec. 7, 2004
6815283 Method of manufacturing semiconductor devices Nov. 9, 2004
6815762 Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines Nov. 9, 2004
6753242 Integrated circuit device and method therefor Jun. 22, 2004
6753222 Method of manufacturing semiconductor device Jun. 22, 2004
6730564 Salicided gate for virtual ground arrays May. 4, 2004
6716701 Method of manufacturing a semiconductor memory device Apr. 6, 2004
6709924 Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate Mar. 23, 2004
6690051 FLASH memory circuitry Feb. 10, 2004
6670227 Method for fabricating devices in core and periphery semiconductor regions using dual spacers Dec. 30, 2003
6633057 Non-volatile semiconductor memory and fabricating method therefor Oct. 14, 2003
6624022 Method of forming FLASH memory Sep. 23, 2003
6621117 Semiconductor device having memory cell and peripheral circuitry with dummy electrode Sep. 16, 2003
6613631 Method of forming a non-volatile semiconductor memory device with a tunnel barrier film defined by side walls Sep. 2, 2003
6541324 Method of forming a semiconductor array of floating gate memory cells having strap regions and a peripheral logic device region Apr. 1, 2003
6528885 Anti-deciphering contacts Mar. 4, 2003
6514830 Method of manufacturing high voltage transistor with modified field implant mask Feb. 4, 2003
6472327 Method and system for etching tunnel oxide to reduce undercutting during memory array fabrication Oct. 29, 2002
6417047 Manufacturing method of a non-volatile semiconductor memory device having isolation regions Jul. 9, 2002
6351017 High voltage transistor with modified field implant mask Feb. 26, 2002
6306707 Double layer hard mask process to improve oxide quality for non-volatile flash memory products Oct. 23, 2001
6294428 Method of forming a flash memory device Sep. 25, 2001
6238975 Method for improving electrostatic discharge (ESD) robustness May. 29, 2001
6235583 Non-volatile semiconductor memory and fabricating method therefor May. 22, 2001
6235587 Method of manufacturing a semiconductor device with reduced arc loss in peripheral circuitry region May. 22, 2001
6207509 Method of manufacturing a semiconductor device Mar. 27, 2001
6184083 Semiconductor device and method of manufacturing the same Feb. 6, 2001
6177312 Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device Jan. 23, 2001
6133096 Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices Oct. 17, 2000
6096602 Method for fabricating flash memory cell Aug. 1, 2000
5834351 Nitridation process with peripheral region protection Nov. 10, 1998

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