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Class Information
Number: 257/E21.678
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Read-only memory structures (rom), i.e., nonvolatile memory structures (epo) > Rom only (epo) > Simultaneous fabrication of periphery and memory cells (epo)
Description: This subclass is indented under subclass E21.667. This subclass is substantially the same in scope as ECLA classification H01L21/8246R8.

Patents under this class:

Patent Number Title Of Patent Date Issued
8574987 Integrating formation of a replacement gate transistor and a non-volatile memory cell using an interlayer dielectric Nov. 5, 2013
8198156 Non-volatile memory device and method for fabricating the same Jun. 12, 2012
8183598 Semiconductor device, semiconductor module, and electronic apparatus including process monitoring pattern overlapping with I/O pad May. 22, 2012
8173505 Method of making a split gate memory cell May. 8, 2012
8105885 Hardened programmable devices Jan. 31, 2012
7977218 Thin oxide dummy tiling as charge protection Jul. 12, 2011
7972929 Method for manufacturing semicondcutor device Jul. 5, 2011
7911005 Dram having deeper source drain region than that of an logic region Mar. 22, 2011
7883952 Method of manufacturing flash memory device Feb. 8, 2011
7851356 Integrated circuit and methods of manufacturing the same Dec. 14, 2010
7772099 Method for manufacturing a semiconductor device having a doped silicon film Aug. 10, 2010
7687847 Semiconductor device and fabricating method thereof Mar. 30, 2010
7651936 Method for patterning a semiconductor device Jan. 26, 2010
7638430 Method of forming contact plug of semiconductor device Dec. 29, 2009
7622348 Methods for fabricating an integrated circuit Nov. 24, 2009
7582550 Semiconductor memory device and manufacturing method thereof Sep. 1, 2009
7390749 Self-aligned pitch reduction Jun. 24, 2008
7314803 Method for producing a semiconductor structure Jan. 1, 2008
7015553 Compact mask programmable ROM Mar. 21, 2006
7012006 Embedded ROM device using substrate leakage Mar. 14, 2006
7001816 Embedded ROM device using substrate leakage Feb. 21, 2006
6699757 Method for manufacturing embedded non-volatile memory with sacrificial layers Mar. 2, 2004
6604234 Method of designing/manufacturing semiconductor integrated circuit device using combined exposure pattern and semiconductor integrated circuit device Aug. 5, 2003
6576517 Method for obtaining a multi-level ROM in an EEPROM process flow Jun. 10, 2003
6573573 Mask ROM and method for fabricating the same Jun. 3, 2003
6521957 Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell Feb. 18, 2003
6518131 Method for fabricating mask ROM Feb. 11, 2003
6514807 Method for fabricating semiconductor device applied system on chip Feb. 4, 2003
6380016 Method for forming programmable CMOS ROM devices Apr. 30, 2002
6323091 Method of forming semiconductor memory device with LDD Nov. 27, 2001
6303442 Mask ROM and method for fabricating the same Oct. 16, 2001
6291308 Mask ROM fabrication method Sep. 18, 2001
6207999 Double coding mask read only memory (mask ROM) for minimizing band-to-band leakage Mar. 27, 2001
6184094 Method for producing semiconductor device Feb. 6, 2001
6177313 Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell Jan. 23, 2001
6150700 Advanced nor-type mask ROM Nov. 21, 2000
6146950 Method of manufacturing multiple metallic layered embedded ROM Nov. 14, 2000
6139992 Photomask used in fabrication of mask read only memory Oct. 31, 2000
6107126 Method to form different threshold NMOSFETS for read only memory devices Aug. 22, 2000
6084275 Double coding mask read only memory (mask ROM) for minimizing band-to-band leakage Jul. 4, 2000
6054353 Short turn around time mask ROM process Apr. 25, 2000
6020241 Post metal code engineering for a ROM Feb. 1, 2000
5960287 Method for manufacturing semiconductor memory devices having a ROM device Sep. 28, 1999
5920784 Method for manufacturing a buried transistor Jul. 6, 1999
5893737 Method for manufacturing semiconductor memory device Apr. 13, 1999
5830772 Method for fabricating isolating regions for buried conductors Nov. 3, 1998
5744394 Method for fabricating a semiconductor device having copper layer Apr. 28, 1998
5308781 Semiconductor memory device May. 3, 1994
5242850 Method of manufacturing a semiconductor memory device having reduced parasitically doped layers Sep. 7, 1993

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