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Class Information
Number: 257/E21.677
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Read-only memory structures (rom), i.e., nonvolatile memory structures (epo) > Rom only (epo) > With fets on different levels, e.g., 3d rom (epo)
Description: This subclass is indented under subclass E21.667. This subclass is substantially the same in scope as ECLA classification H01L21/8246R6.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 8486791 |
Mufti-layer single crystal 3D stackable memory |
Jul. 16, 2013 |
| 8377817 |
Three dimensional semiconductor memory device and method of manufacturing the same |
Feb. 19, 2013 |
| 8247860 |
Nonvolatile semiconductor memory device and method for manufacturing same |
Aug. 21, 2012 |
| 7972955 |
Three dimensional semiconductor memory device and method of fabricating the same |
Jul. 5, 2011 |
| 7915164 |
Method for forming doped polysilicon via connecting polysilicon layers |
Mar. 29, 2011 |
| 7915163 |
Method for forming doped polysilicon via connecting polysilicon layers |
Mar. 29, 2011 |
| 7626257 |
Semiconductor devices and methods of manufacture thereof |
Dec. 1, 2009 |
| 7442997 |
Three-dimensional memory cells |
Oct. 28, 2008 |
| 6841813 |
TFT mask ROM and method for making same |
Jan. 11, 2005 |
| 6737711 |
Semiconductor device with bit lines formed via diffusion over word lines |
May. 18, 2004 |
| 6180458 |
Method of producing a memory cell configuration |
Jan. 30, 2001 |
| 6064101 |
Read-only memory cell arrangement |
May. 16, 2000 |
| 5952697 |
Multiple storage planes Read Only Memory integrated circuit device |
Sep. 14, 1999 |
| 5893738 |
Method for forming double density MROM array structure |
Apr. 13, 1999 |
| 5891779 |
Method of fabricating tetra-state mask read only memory |
Apr. 6, 1999 |
| 5858841 |
ROM device having memory units arranged in three dimensions, and a method of making the same |
Jan. 12, 1999 |
| 5828113 |
Double density MROM array structure |
Oct. 27, 1998 |
| 5763925 |
ROM device having memory units arranged in three dimensions, and a method of making the same |
Jun. 9, 1998 |
| 5751040 |
Self-aligned source/drain mask ROM memory cell using trench etched channel |
May. 12, 1998 |
| 5721169 |
Multiple storage planes read only memory integrated circuit device and method of manufacture thereof |
Feb. 24, 1998 |
| 5693552 |
Method for fabricating read-only memory device with a three-dimensional memory cell structure |
Dec. 2, 1997 |
| 5306941 |
Semiconductor memory device and production process thereof |
Apr. 26, 1994 |
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