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Class Information
Number: 257/E21.676
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Read-only memory structures (rom), i.e., nonvolatile memory structures (epo) > Rom only (epo) > With source and drain on different levels, e.g., vertical channel (epo)
Description: This subclass is indented under subclass E21.667. This subclass is substantially the same in scope as ECLA classification H01L21/8246R4.

Patents under this class:
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Patent Number Title Of Patent Date Issued
8614469 Semiconductor device and manufacturing method of the same Dec. 24, 2013
8450176 Methods of manufacturing rewriteable three-dimensional semiconductor memory devices May. 28, 2013
8435855 Methods of manufacturing semiconductor devices May. 7, 2013
8394690 Semiconductor device and fabrication method thereof Mar. 12, 2013
8309417 Vertical-type semiconductor devices and methods of manufacturing the same Nov. 13, 2012
8268687 Three-dimensional semiconductor memory device and method of fabricating the same Sep. 18, 2012
8119484 DRAM with nanofin transistors Feb. 21, 2012
8105904 Method of manufacturing semiconductor devices Jan. 31, 2012
7989292 Method of fabricating a semiconductor device with a channel formed in a vertical direction Aug. 2, 2011
7960796 Semiconductor device having element isolation region Jun. 14, 2011
7838913 Hybrid FET incorporating a finFET and a planar FET Nov. 23, 2010
7829415 Method of fabricating semiconductor device for preventing a pillar pattern from bending and from exposing externally Nov. 9, 2010
7709889 Semiconductor device with improved breakdown properties and manufacturing method thereof May. 4, 2010
7592224 Method of fabricating a storage device including decontinuous storage elements within and between trenches Sep. 22, 2009
7586130 Vertical field effect transistor using linear structure as a channel region and method for fabricating the same Sep. 8, 2009
7510924 Method for manufacturing memory cell Mar. 31, 2009
7462530 Method for manufacturing a semiconductor device having an element isolation region Dec. 9, 2008
7339239 Vertical NROM NAND flash memory array Mar. 4, 2008
7276754 Annular gate and technique for fabricating an annular gate Oct. 2, 2007
7268379 Memory cell and method for manufacturing the same Sep. 11, 2007
7242050 Stacked gate memory cell with erase to gate, array, and method of manufacturing Jul. 10, 2007
6750095 Integrated circuit with vertical transistors Jun. 15, 2004
6621129 MROM memory cell structure for storing multi level bit information Sep. 16, 2003
6475866 Method for production of a memory cell arrangement Nov. 5, 2002
6472696 Memory cell configuration and corresponding production process Oct. 29, 2002
6429494 Semiconductor read-only memory and method of manufacturing the same Aug. 6, 2002
6303436 Method for fabricating a type of trench mask ROM cell Oct. 16, 2001
6281557 Read-only memory cell array and method for fabricating it Aug. 28, 2001
6265748 Storage cell arrangement in which vertical MOS transistors have at least three different threshold voltages depending on stored data, and method of producing said arrangement Jul. 24, 2001
6235592 Type of high density vertical Mask ROM cell May. 22, 2001
6180979 Memory cell arrangement with vertical MOS transistors and the production process thereof Jan. 30, 2001
6157069 Highly integrated mask ROM for coding data Dec. 5, 2000
6043543 Read-only memory cell configuration with trench MOS transistor and widened drain region Mar. 28, 2000
6022779 Method of forming mask ROM Feb. 8, 2000
5994746 Memory cell configuration and method for its fabrication Nov. 30, 1999
5973373 Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of different thicknesses and method for its production Oct. 26, 1999
5920778 Read-only memory cell arrangement and method for its production Jul. 6, 1999
5877537 Semiconductor device having first transistor rows with second transistor rows connected therebetween Mar. 2, 1999
5747856 Vertical channel masked ROM memory cell with epitaxy May. 5, 1998
5595927 Method for making self-aligned source/drain mask ROM memory cell using trench etched channel Jan. 21, 1997
5510287 Method of making vertical channel mask ROM Apr. 23, 1996
5455435 Late programming mask ROM and process for producing the same Oct. 3, 1995
5426066 Late programming mask ROM and process for producing the same Jun. 20, 1995
5418178 High-density read-only memory fabrication May. 23, 1995
5372964 Method of producing pillar-shaped DRAM and ROM devices Dec. 13, 1994
5300804 Mask ROM device having highly integrated memory cell structure Apr. 5, 1994
5057896 Semiconductor device and method of producing same Oct. 15, 1991
4663644 Semiconductor device and method of manufacturing the same May. 5, 1987
4390971 Post-metal programmable MOS read only memory Jun. 28, 1983
4385432 Closely-spaced double level conductors for MOS read only May. 31, 1983

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