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Class Information
Number: 257/E21.671
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Read-only memory structures (rom), i.e., nonvolatile memory structures (epo) > Rom only (epo) > With source and drain on same level, e.g., lateral channel (epo) > Doping programmed, e.g., mask rom (epo)
Description: This subclass is indented under subclass E21.668. This subclass is substantially the same in scope as ECLA classification H01L21/8246R2D.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.672 Entire channel doping programmed (epo) 209
257/E21.673 Source or drain doping programmed (epo) 70


Patents under this class:
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Patent Number Title Of Patent Date Issued
8455342 Mask ROM fabrication method Jun. 4, 2013
8415218 Atomic layer deposition epitaxial silicon growth for TFT flash memory cell Apr. 9, 2013
7645672 Mask ROM, method for fabricating the same, and method for coding the same Jan. 12, 2010
7358120 Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM Apr. 15, 2008
7250646 TFT mask ROM and method for making same Jul. 31, 2007
7227233 Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM Jun. 5, 2007
7094649 Method for forming multi-level mask ROM cell and NAND multi-level mask ROM Aug. 22, 2006
7005693 Semiconductor memory device for storing data in memory cells as complementary information Feb. 28, 2006
6919607 Structure of two-bit mask read-only memory device and fabricating method thereof Jul. 19, 2005
6908854 Method of forming a dual-layer resist and application thereof Jun. 21, 2005
6908819 Method of fabricating flat-cell mask read-only memory devices Jun. 21, 2005
6902979 Method for manufacturing mask ROM Jun. 7, 2005
6839278 Highly-integrated flash memory and mask ROM array architecture Jan. 4, 2005
6821841 Method for fabricating a mask read-only-memory with diode cells Nov. 23, 2004
6807112 Mask programmable read only memory Oct. 19, 2004
6803284 Method for manufacturing embedded non-volatile memory with two polysilicon layers Oct. 12, 2004
6794253 Mask ROM structure and method of fabricating the same Sep. 21, 2004
6790730 Fabrication method for mask read only memory device Sep. 14, 2004
6773937 Method of verifying a mask for a mask ROM Aug. 10, 2004
6734508 Mask ROM, and fabrication method thereof May. 11, 2004
6716704 Methods of fabricating read only memory devices including thermally oxidized transistor sidewalls Apr. 6, 2004
6709933 Method of fabricating mask ROM Mar. 23, 2004
6706575 Method for fabricating a non-volatile memory Mar. 16, 2004
6699757 Method for manufacturing embedded non-volatile memory with sacrificial layers Mar. 2, 2004
6693309 Mask ROM and method for manufacturing the same Feb. 17, 2004
6673682 Methods of fabricating high density mask ROM cells Jan. 6, 2004
6670103 Method for forming lightly doped diffusion regions Dec. 30, 2003
6617633 Vertical read-only memory and fabrication thereof Sep. 9, 2003
6599680 Method for forming cells array of mask read only memory Jul. 29, 2003
6586303 Method for fabricating a mask ROM Jul. 1, 2003
6570235 Cells array of mask read only memory May. 27, 2003
6521957 Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell Feb. 18, 2003
6512277 Semiconductor memory device and fabrication thereof Jan. 28, 2003
6489251 Method of forming a slope lateral structure Dec. 3, 2002
6482702 Method of forming and recognizing an identification mark for read-only memory Nov. 19, 2002
6479874 Semiconductor memory device having multilevel memory cell and method of manufacturing the same Nov. 12, 2002
6388910 NOR type mask ROM with an increased data flow rate May. 14, 2002
6376887 Semiconductor memory having buried digit lines Apr. 23, 2002
6297537 Semiconductor device and method for production thereof Oct. 2, 2001
6259143 Semiconductor memory device of NOR type mask ROM and manufacturing method of the same Jul. 10, 2001
6207999 Double coding mask read only memory (mask ROM) for minimizing band-to-band leakage Mar. 27, 2001
6204127 Method of manufacturing bit lines in memory Mar. 20, 2001
6190974 Method of fabricating a mask ROM Feb. 20, 2001
6177313 Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell Jan. 23, 2001
6177693 Semiconductor device Jan. 23, 2001
6165850 Method of manufacturing mask read-only-memory Dec. 26, 2000
6136683 Semiconductor device and method for production thereof Oct. 24, 2000
6133102 Method of fabricating double poly-gate high density multi-state flat mask ROM cells Oct. 17, 2000
6121664 Semiconductor memory device Sep. 19, 2000
6084275 Double coding mask read only memory (mask ROM) for minimizing band-to-band leakage Jul. 4, 2000

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