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Class Information
Number: 257/E21.67
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Read-only memory structures (rom), i.e., nonvolatile memory structures (epo) > Rom only (epo) > With source and drain on same level, e.g., lateral channel (epo) > Gate contact programmed (epo)
Description: This subclass is indented under subclass E21.668. This subclass is substantially the same in scope as ECLA classification H01L21/8246R2C.










Patents under this class:

Patent Number Title Of Patent Date Issued
8501503 Methods of inspecting and manufacturing semiconductor wafers Aug. 6, 2013
8105885 Hardened programmable devices Jan. 31, 2012
8106463 Memory cells for read only memories Jan. 31, 2012
8089121 Nonvolatile semiconductor memory device and method of manufacturing the same Jan. 3, 2012
8053342 Mask ROM device, semiconductor device including the mask ROM device, and methods of fabricating mask ROM device and semiconductor device Nov. 8, 2011
7888217 Method for fabricating a gate dielectric of a field effect transistor Feb. 15, 2011
7064035 Mask ROM and fabrication thereof Jun. 20, 2006
6777762 Mask ROM structure having a coding layer between gates and word lines Aug. 17, 2004
6194274 Method of fabricating a mask ROM Feb. 27, 2001
6150198 Method of fabricating semiconductor read-only memory device with reduced parastic capacitance between bit line and word line Nov. 21, 2000
5946576 Method of fabricating a semiconductor ready-only memory device used for permanent storage of multi-level coded data Aug. 31, 1999
5895241 Method for fabricating a cell structure for mask ROM Apr. 20, 1999
5834819 Semiconductor read-only memory device for permanent storage of multi-level coded data Nov. 10, 1998
5812448 Semiconductor read-only memory device and method of fabricating the same Sep. 22, 1998
5811337 Method of fabricating a semiconductor read-only memory device for permanent storage of multi-level coded data Sep. 22, 1998
5792697 Method for fabricating a multi-stage ROM Aug. 11, 1998
5650960 Polysilicon programming memory cell Jul. 22, 1997
5594684 Polysilicon programming memory cell Jan. 14, 1997
5512507 Process for post metal coding of a ROM, by gate etch Apr. 30, 1996
5494842 Method of programming a CMOS read only memory at the second metal layer in a two-metal process Feb. 27, 1996
4180826 MOS double polysilicon read-only memory and cell Dec. 25, 1979
4176442 Method for producing a semiconductor fixed value ROM Dec. 4, 1979











 
 
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