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Class Information
Number: 257/E21.668
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Read-only memory structures (rom), i.e., nonvolatile memory structures (epo) > Rom only (epo) > With source and drain on same level, e.g., lateral channel (epo)
Description: This subclass is indented under subclass E21.667. This subclass is substantially the same in scope as ECLA classification H01L21/8246R2.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.671 Doping programmed, e.g., mask rom (epo) 63
257/E21.67 Gate contact programmed (epo) 22
257/E21.675 Gate dielectric programmed, e.g., different thickness (epo) 42
257/E21.674 Gate programmed, e.g., different gate material or no gate (epo) 17
257/E21.669 Source or drain contact programmed (epo) 34


Patents under this class:

Patent Number Title Of Patent Date Issued
8658526 Methods for increased array feature density Feb. 25, 2014
8575015 Lateral trench mosfet having a field plate Nov. 5, 2013
8357606 Resist feature and removable spacer pitch doubling patterning method for pillar structures Jan. 22, 2013
7550344 Semiconductor device and method for fabricating the same Jun. 23, 2009
7402476 Method for forming an electronic device Jul. 22, 2008
6906940 Plane decoding method and device for three dimensional memories Jun. 14, 2005
6831335 Memory device having buried source/drain region and fabrication thereof Dec. 14, 2004
6800524 Method of manufacturing semiconductor integrated circuit device Oct. 5, 2004
6717208 Disabling flash memory to protect memory contents Apr. 6, 2004
6688969 Method for planarizing a dielectric layer of a flash memory device Feb. 10, 2004
6645816 Fabricating memory device having buried source/drain region and fabrication thereof Nov. 11, 2003
6489251 Method of forming a slope lateral structure Dec. 3, 2002
6410385 ROM-embedded-DRAM Jun. 25, 2002
6303463 Method for fabricating a flat-cell semiconductor memory device Oct. 16, 2001
6243285 ROM-embedded-DRAM Jun. 5, 2001
6194275 Method to form a mask ROM device with coding after source and drain implantation Feb. 27, 2001
6190950 Dense SOI programmable logic array structure Feb. 20, 2001
6187637 Method for increasing isolation ability using shallow trench Feb. 13, 2001
6134137 Rom-embedded-DRAM Oct. 17, 2000
6077746 Using p-type halo implant as ROM cell isolation in flat-cell mask ROM process Jun. 20, 2000
6051469 Method of fabricating bit line Apr. 18, 2000
5998287 Process for producing very narrow buried bit lines for non-volatile memory devices Dec. 7, 1999
5960287 Method for manufacturing semiconductor memory devices having a ROM device Sep. 28, 1999
5946577 Method of manufacturing semiconductor device Aug. 31, 1999
5852317 Method to reduce gate oxide damage due to non-uniform plasmas in read only memory arrays Dec. 22, 1998
5652162 Method for fabricating flat ROM devices using memory array cells with concave channels Jul. 29, 1997
5429988 Process for producing high density conductive lines Jul. 4, 1995
5418176 Process for producing memory devices having narrow buried N+ lines May. 23, 1995
5378646 Process for producing closely spaced conductive lines for integrated circuits Jan. 3, 1995
5318921 Method for making a high density ROM or EPROM integrated circuit Jun. 7, 1994
4981812 Process for fabricating a semiconductor read only memory Jan. 1, 1991











 
 
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