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Class Information
Number: 257/E21.653
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Characterized by type of capacitor (epo) > Capacitor stacked over transfer transis tor (epo) > Capacitor in u- or v-shaped trench in substrate (epo) > Making connection between transistor and capacitor, e.g., buried strap (epo)
Description: This subclass is indented under subclass E21.651. This subclass is substantially the same in scope as ECLA classification H01L21/8242B6C.










Patents under this class:
1 2 3 4

Patent Number Title Of Patent Date Issued
8575670 Embedded dynamic random access memory device formed in an extremely thin semiconductor on insulator (ETSOI) substrate Nov. 5, 2013
8492820 Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit Jul. 23, 2013
8410534 Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact Apr. 2, 2013
8133781 Method of forming a buried plate by ion implantation Mar. 13, 2012
8129772 Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact Mar. 6, 2012
8053823 Simplified buried plate structure and process for semiconductor-on-insulator chip Nov. 8, 2011
7879672 eDRAM memory cell structure and method of fabricating Feb. 1, 2011
7863677 Semiconductor device and method of fabricating the same Jan. 4, 2011
7763519 Method for fabricating an interconnect arrangement with increased capacitive coupling and associated interconnect arrangement Jul. 27, 2010
7670902 Method and structure for landing polysilicon contact Mar. 2, 2010
7608510 Alignment of trench for MOS Oct. 27, 2009
7563669 Integrated circuit with a trench capacitor structure and method of manufacture Jul. 21, 2009
7553723 Manufacturing method of a memory device Jun. 30, 2009
7553737 Method for fabricating recessed-gate MOS transistor device Jun. 30, 2009
7518175 Semiconductor memory device and method for fabricating the same Apr. 14, 2009
7491603 Transistors of semiconductor device having channel region in a channel-portion hole and methods of forming the same Feb. 17, 2009
7439135 Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same Oct. 21, 2008
7276752 Methods of forming integrated circuits, and DRAM circuitry memory cells Oct. 2, 2007
7262092 High-voltage CMOS-compatible capacitors Aug. 28, 2007
7223651 Dram memory cell with a trench capacitor and method for production thereof May. 29, 2007
7208373 Method of forming a memory cell array and a memory cell array Apr. 24, 2007
7195973 Method for fabricating a trench capacitor with an insulation collar and corresponding trench capacitor Mar. 27, 2007
7192825 Semiconductor memory device and method for fabricating the same Mar. 20, 2007
7074689 Method for fabricating a trench capacitor having an insulation collar, which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory Jul. 11, 2006
7067372 Method for fabricating a memory cell having a trench Jun. 27, 2006
7041568 Method for the production of a self-adjusted structure on a semiconductor wafer May. 9, 2006
7015145 Self-aligned collar and strap formation for semiconductor devices Mar. 21, 2006
6989311 Method for fabricating a trench contact to a deep trench capacitor having a polysilicon filling Jan. 24, 2006
6977405 Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it Dec. 20, 2005
6974988 DRAM cell structure capable of high integration and fabrication method thereof Dec. 13, 2005
6953722 Method for patterning ceramic layers Oct. 11, 2005
6946345 Self-aligned buried strap process using doped HDP oxide Sep. 20, 2005
6946700 Trench DRAM cell with vertical device and buried word lines Sep. 20, 2005
6916721 Method for fabricating a trench capacitor with an insulation collar Jul. 12, 2005
6906372 Semiconductor device with vertical transistor formed in a silicon-on-insulator substrate Jun. 14, 2005
6897107 Method for forming TTO nitride liner for improved collar protection and TTO reliability May. 24, 2005
6872620 Trench capacitors with reduced polysilicon stress Mar. 29, 2005
6873000 Storage cell field and method of producing the same Mar. 29, 2005
6849496 DRAM with vertical transistor and trench capacitor memory cells and method of fabrication Feb. 1, 2005
6849890 Semiconductor device and manufacturing method thereof Feb. 1, 2005
6838335 Method for fabricating a vertical transistor, and semiconductor memory cell having a trench capacitor and an associated vertical selection transistor Jan. 4, 2005
6833302 Method for fabricating a memory cell Dec. 21, 2004
6828615 Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices Dec. 7, 2004
6828192 Semiconductor memory cell and method for fabricating the memory cell Dec. 7, 2004
6821861 Method for fabricating an electrode arrangement for charge storage Nov. 23, 2004
6818501 Method of making a self-aligned recessed container cell capacitor Nov. 16, 2004
6815749 Backside buried strap for SOI DRAM trench capacitor Nov. 9, 2004
6812093 Method for fabricating memory cell structure employing contiguous gate and capacitor dielectric layer Nov. 2, 2004
6809368 TTO nitride liner for improved collar protection and TTO reliability Oct. 26, 2004
6797562 Method for manufacturing a buried strap contact in a memory cell Sep. 28, 2004

1 2 3 4










 
 
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