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Class Information
Number: 257/E21.652
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Characterized by type of capacitor (epo) > Capacitor stacked over transfer transis tor (epo) > Capacitor in u- or v-shaped trench in substrate (epo) > In combination with vertical transistor (epo)
Description: This subclass is indented under subclass E21.651. This subclass is substantially the same in scope as ECLA classification H01L21/8242B6B.

Patents under this class:
1 2 3 4 5 6

Patent Number Title Of Patent Date Issued
6635526 Structure and method for dual work function logic devices in vertical DRAM process Oct. 21, 2003
6630379 Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch Oct. 7, 2003
6624033 Trench DRAM cell with vertical device and buried word lines Sep. 23, 2003
6620699 Method for forming inside nitride spacer for deep trench device DRAM cell Sep. 16, 2003
6610573 Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate Aug. 26, 2003
6610566 Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor Aug. 26, 2003
6608340 Substrate assembly having a depression suitable for an integrated circuit configuration and method for its fabrication Aug. 19, 2003
6605838 Process flow for thick isolation collar with reduced length Aug. 12, 2003
6605504 Method of manufacturing circuit with buried strap including a liner Aug. 12, 2003
6605860 Semiconductor structures and manufacturing methods Aug. 12, 2003
6590259 Semiconductor device of an embedded DRAM on SOI substrate Jul. 8, 2003
6586795 DRAM cell configuration whose memory cells can have transistors and capacitors with improved electrical properties Jul. 1, 2003
6583462 Vertical DRAM having metallic node conductor Jun. 24, 2003
6576944 Self-aligned nitride pattern for improved process window Jun. 10, 2003
6576945 Structure and method for a compact trench-capacitor DRAM cell with body contact Jun. 10, 2003
6573137 Single sided buried strap Jun. 3, 2003
6573136 Isolating a vertical gate contact structure Jun. 3, 2003
6573561 Vertical MOSFET with asymmetrically graded channel doping Jun. 3, 2003
6570208 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI May. 27, 2003
6570207 Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex May. 27, 2003
6566227 Strap resistance using selective oxidation to cap DT poly before STI etch May. 20, 2003
6566177 Silicon-on-insulator vertical array device trench capacitor DRAM May. 20, 2003
6566187 DRAM cell system and method for producing same May. 20, 2003
6566190 Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices May. 20, 2003
6566193 Method for producing a cell of a semiconductor memory May. 20, 2003
6566219 Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening May. 20, 2003
6555862 Self-aligned buried strap for vertical transistors Apr. 29, 2003
6552382 Scalable vertical DRAM cell structure and its manufacturing methods Apr. 22, 2003
6548344 Spacer formation process using oxide shield Apr. 15, 2003
6541810 Modified vertical MOSFET and methods of formation thereof Apr. 1, 2003
6537870 Method of forming an integrated circuit comprising a self aligned trench Mar. 25, 2003
6537871 Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor Mar. 25, 2003
6537872 Method of fabricating a DRAM cell capacitor Mar. 25, 2003
6534824 Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell Mar. 18, 2003
6534359 Method of fabricating memory cell Mar. 18, 2003
6528837 Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor Mar. 4, 2003
6521935 Mos transistor and dram cell configuration Feb. 18, 2003
6518613 Memory cell configuration with capacitor on opposite surface of substrate and method for fabricating the same Feb. 11, 2003
6518616 Vertical gate top engineering for improved GC and CB process windows Feb. 11, 2003
6515327 Trench capacitor with expanded area and method of making the same Feb. 4, 2003
6501117 Static self-refreshing DRAM structure and operating mode Dec. 31, 2002
6500707 Method for manufacturing a trench capacitor of a memory cell of a semiconductor memory Dec. 31, 2002
6492233 Memory cell with vertical transistor and buried word and body lines Dec. 10, 2002
6492221 DRAM cell arrangement Dec. 10, 2002
6452224 Method for manufacture of improved deep trench eDRAM capacitor and structure produced thereby Sep. 17, 2002
6448610 Memory cell with trench, and method for production thereof Sep. 10, 2002
6441422 Structure and method for ultra-scalable hybrid DRAM cell with contacted P-well Aug. 27, 2002
6436836 Method of fabricating a DRAM cell configuration Aug. 20, 2002
6437381 Semiconductor memory device with reduced orientation-dependent oxidation in trench structures Aug. 20, 2002
6437388 Compact trench capacitor memory cell with body contact Aug. 20, 2002

1 2 3 4 5 6

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