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Class Information
Number: 257/E21.652
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Characterized by type of capacitor (epo) > Capacitor stacked over transfer transis tor (epo) > Capacitor in u- or v-shaped trench in substrate (epo) > In combination with vertical transistor (epo)
Description: This subclass is indented under subclass E21.651. This subclass is substantially the same in scope as ECLA classification H01L21/8242B6B.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7611931 |
Semiconductor structures with body contacts and fabrication methods thereof |
Nov. 3, 2009 |
| 7608510 |
Alignment of trench for MOS |
Oct. 27, 2009 |
| 7563670 |
Method for etching single-crystal semiconductor selective to amorphous/polycrystalline semiconductor and structure formed by same |
Jul. 21, 2009 |
| 7563686 |
Method for forming a memory device with a recessed gate |
Jul. 21, 2009 |
| 7547604 |
Method of forming a recessed gate structure on a substrate having insulating columns and removing said insulating columns after forming a conductive region of the gate structure |
Jun. 16, 2009 |
| 7485525 |
Method of manufacturing a multiple port memory having a plurality of parallel connected trench capacitors in a cell |
Feb. 3, 2009 |
| 7482229 |
DRAM cells with vertical transistors |
Jan. 27, 2009 |
| 7445986 |
Memory cells with vertical transistor and capacitor and fabrication methods thereof |
Nov. 4, 2008 |
| 7439135 |
Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same |
Oct. 21, 2008 |
| 7429509 |
Method for forming a semiconductor device |
Sep. 30, 2008 |
| 7394124 |
Dynamic random access memory device |
Jul. 1, 2008 |
| 7364997 |
Methods of forming integrated circuitry and methods of forming local interconnects |
Apr. 29, 2008 |
| 7358133 |
Semiconductor device and method for making the same |
Apr. 15, 2008 |
| 7354822 |
Method of forming a MOSFET with dual work function materials |
Apr. 8, 2008 |
| 7316953 |
Method for forming a recessed gate with word lines |
Jan. 8, 2008 |
| 7316952 |
Method for forming a memory device with a recessed gate |
Jan. 8, 2008 |
| 7276754 |
Annular gate and technique for fabricating an annular gate |
Oct. 2, 2007 |
| 7229872 |
Low voltage power MOSFET device and process for its manufacture |
Jun. 12, 2007 |
| 7115934 |
Method and structure for enhancing trench capacitance |
Oct. 3, 2006 |
| 7067372 |
Method for fabricating a memory cell having a trench |
Jun. 27, 2006 |
| 7057224 |
Semiconductor memory having an arrangement of memory cells |
Jun. 6, 2006 |
| 7057223 |
Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor |
Jun. 6, 2006 |
| 7049196 |
Vertical gain cell and array for a dynamic random access memory and method for forming the same |
May. 23, 2006 |
| 7015526 |
Dynamic memory cell and method of manufacturing same |
Mar. 21, 2006 |
| 7015145 |
Self-aligned collar and strap formation for semiconductor devices |
Mar. 21, 2006 |
| 7009869 |
Dynamic memory cell |
Mar. 7, 2006 |
| 7005346 |
Method for producing a memory cell of a memory cell field in a semiconductor memory |
Feb. 28, 2006 |
| 6987043 |
Method of manufacturing semiconductor device having a plurality of trench-type data storage capacitors |
Jan. 17, 2006 |
| 6977405 |
Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it |
Dec. 20, 2005 |
| 6974988 |
DRAM cell structure capable of high integration and fabrication method thereof |
Dec. 13, 2005 |
| 6946700 |
Trench DRAM cell with vertical device and buried word lines |
Sep. 20, 2005 |
| 6946345 |
Self-aligned buried strap process using doped HDP oxide |
Sep. 20, 2005 |
| 6936484 |
Method of manufacturing semiconductor device and semiconductor device |
Aug. 30, 2005 |
| 6909136 |
Trench-capacitor DRAM cell having a folded gate conductor |
Jun. 21, 2005 |
| 6906372 |
Semiconductor device with vertical transistor formed in a silicon-on-insulator substrate |
Jun. 14, 2005 |
| 6897107 |
Method for forming TTO nitride liner for improved collar protection and TTO reliability |
May. 24, 2005 |
| 6887749 |
Multiple oxide thicknesses for merged memory and logic applications |
May. 3, 2005 |
| 6873000 |
Storage cell field and method of producing the same |
Mar. 29, 2005 |
| 6873010 |
High performance logic and high density embedded dram with borderless contact and antispacer |
Mar. 29, 2005 |
| 6853023 |
Semiconductor memory cell configuration and a method for producing the configuration |
Feb. 8, 2005 |
| 6838335 |
Method for fabricating a vertical transistor, and semiconductor memory cell having a trench capacitor and an associated vertical selection transistor |
Jan. 4, 2005 |
| 6833305 |
Vertical DRAM punchthrough stop self-aligned to storage trench |
Dec. 21, 2004 |
| 6828615 |
Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices |
Dec. 7, 2004 |
| 6825093 |
Process window enhancement for deep trench spacer conservation |
Nov. 30, 2004 |
| 6822281 |
Trench cell for a DRAM cell array |
Nov. 23, 2004 |
| 6821843 |
Fabrication method for an array area and a support area of a dynamic random access memory |
Nov. 23, 2004 |
| 6812092 |
Method for fabricating transistors having damascene formed gate contacts and self-aligned borderless bit line contacts |
Nov. 2, 2004 |
| 6809368 |
TTO nitride liner for improved collar protection and TTO reliability |
Oct. 26, 2004 |
| 6808981 |
Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI |
Oct. 26, 2004 |
| 6808979 |
Method for forming vertical transistor and trench capacitor |
Oct. 26, 2004 |
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