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Browse by Category: Main > Physics
Class Information
Number: 257/E21.65
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Dynamic random access memory structures (dram) (epo) > Characterized by type of capacitor (epo) > Capacitor stacked over transfer transis tor (epo) > Capacitor extending under transfer transistor area (epo)
Description: This subclass is indented under subclass E21.647. This subclass is substantially the same in scope as ECLA classification H01L21/8242B4.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8637364 Semiconductor device and method of manufacturing the same Jan. 28, 2014
8410534 Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact Apr. 2, 2013
8294189 Memory device and fabrication method thereof Oct. 23, 2012
8129772 Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact Mar. 6, 2012
7807517 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions Oct. 5, 2010
7709878 Capacitor structure having butting conductive layer May. 4, 2010
7642107 Split transfer gate for dark current suppression an imager pixel Jan. 5, 2010
7563667 Method for fabricating semiconductor device Jul. 21, 2009
7507629 Semiconductor devices having an interfacial dielectric layer and related methods Mar. 24, 2009
7491604 Trench memory with monolithic conducting material and methods for forming same Feb. 17, 2009
7052997 Method to form etch and/or CMP stop layers May. 30, 2006
6939763 DRAM cell arrangement with vertical MOS transistors, and method for its fabrication Sep. 6, 2005
6790726 Method for producing an integrated semiconductor memory configuration Sep. 14, 2004
6777306 Memory cell capacitors having an over/under configuration Aug. 17, 2004
6774422 Memory cell capacitors having an over/under configuration Aug. 10, 2004
6734062 Methods of forming DRAM cells May. 11, 2004
6706608 Memory cell capacitors having an over/under configuration Mar. 16, 2004
6707090 DRAM cell constructions Mar. 16, 2004
6639243 DRAM cell constructions Oct. 28, 2003
6620672 SOI DRAM with buried capacitor under the digit lines utilizing a self aligning penetrating storage node contact formation Sep. 16, 2003
6605508 Semiconductor device and method of manufacturing thereof Aug. 12, 2003
6569734 Method for two-sided fabrication of a memory array May. 27, 2003
6569733 Gate device with raised channel and method May. 27, 2003
6566182 DRAM memory cell for DRAM memory device and method for manufacturing it May. 20, 2003
6465331 DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines Oct. 15, 2002
6433376 Ferroelectric memory integrated circuit Aug. 13, 2002
6429070 DRAM cell constructions, and methods of forming DRAM cells Aug. 6, 2002
6429069 SOI DRAM with buried capacitor under the digit lines utilizing a self aligning penetrating storage node contact formation Aug. 6, 2002
6423596 Method for two-sided fabrication of a memory array Jul. 23, 2002
6410379 Method of forming a submerged semiconductor structure Jun. 25, 2002
6380028 Semiconductor device and a method of manufacturing thereof Apr. 30, 2002
6352890 Method of forming a memory cell with self-aligned contacts Mar. 5, 2002
6348706 Method to form etch and/or CMP stop layers Feb. 19, 2002
6335896 Dynamic random access memory Jan. 1, 2002
6330181 Method of forming a gate device with raised channel Dec. 11, 2001
6306719 Method for manufacturing a semiconductor device Oct. 23, 2001
6300179 Gate device with access channel formed in discrete post and method Oct. 9, 2001
6297090 Method for fabricating a high-density semiconductor memory device Oct. 2, 2001
6242319 Method for fabricating an integrated circuit configuration Jun. 5, 2001
6242298 Semiconductor memory device having epitaxial planar capacitor and method for manufacturing the same Jun. 5, 2001
6218232 Method for fabricating DRAM device Apr. 17, 2001
6211531 Controllable conduction device Apr. 3, 2001
6181014 Integrated circuit memory devices having highly integrated SOI memory cells therein Jan. 30, 2001
6169308 Semiconductor memory device and manufacturing method thereof Jan. 2, 2001
6165837 Semiconductor integrated memory manufacturing method and device Dec. 26, 2000
6072208 Dynamic random access memory fabricated with SOI substrate Jun. 6, 2000
6060723 Controllable conduction device May. 9, 2000
6015990 Semiconductor memory device and method of manufacturing the same Jan. 18, 2000
5968840 Dynamic random access memory using silicon-on-insulator techniques Oct. 19, 1999
5959322 Isolated SOI memory structure with vertically formed transistor and storage capacitor in a substrate Sep. 28, 1999

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