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Class Information
Number: 257/E21.634
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Complementary field-effect transistors, e.g., cmos (epo) > With particular manufacturing method of source or drain, e.g., specific s or d implants or silicided s or d structures or raised s or d structures (epo)
Description: This subclass is indented under subclass E21.632. This subclass is substantially the same in scope as ECLA classification H01L21/8238D.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8709883 Implant for performance enhancement of selected transistors in an integrated circuit Apr. 29, 2014
8710538 Light-emitting device with a spacer at bottom surface Apr. 29, 2014
8673713 Method for forming a transistor with recessed drain and source areas and non-conformal metal silicide regions Mar. 18, 2014
8664073 Method for fabricating field-effect transistor Mar. 4, 2014
8664068 Low-diffusion drain and source regions in CMOS transistors for low power/high performance applications Mar. 4, 2014
8652915 Methods of fabricating semiconductor devices using preliminary trenches with epitaxial growth Feb. 18, 2014
8642434 Structure and method for mobility enhanced MOSFETS with unalloyed silicide Feb. 4, 2014
8642420 Fabrication of a semiconductor device with extended epitaxial semiconductor regions Feb. 4, 2014
8642435 Performing treatment on stressors Feb. 4, 2014
8633070 Lightly doped source/drain last method for dual-epi integration Jan. 21, 2014
8610233 Hybrid MOSFET structure having drain side schottky junction Dec. 17, 2013
8598003 Semiconductor device having doped epitaxial region and its methods of fabrication Dec. 3, 2013
8536032 Formation of embedded stressor through ion implantation Sep. 17, 2013
8536619 Strained MOS device and methods for forming the same Sep. 17, 2013
8530315 finFET with fully silicided gate Sep. 10, 2013
8524566 Methods for the fabrication of integrated circuits including back-etching of raised conductive structures Sep. 3, 2013
8507338 Semiconductor structure and fabricating method thereof Aug. 13, 2013
8497179 Method of fabricating multi-fingered semiconductor devices on a common substrate Jul. 30, 2013
8486794 Method for manufacturing semiconductor structure Jul. 16, 2013
8486783 Semiconductor device and method of manufacturing the same Jul. 16, 2013
8476154 Method of making a charge trapping non-volatile semiconductor memory device Jul. 2, 2013
8470707 Silicide method Jun. 25, 2013
8460990 CMOS transistor using germanium condensation and method of fabricating the same Jun. 11, 2013
8460981 Use of contacts to create differential stresses on devices Jun. 11, 2013
8455930 Strained semiconductor device with facets Jun. 4, 2013
8435855 Methods of manufacturing semiconductor devices May. 7, 2013
8431462 Methods of manufacturing semiconductor devices Apr. 30, 2013
8426298 CMOS devices with Schottky source and drain regions Apr. 23, 2013
8421159 Raised source/drain field effect transistor Apr. 16, 2013
8409958 Method of manufacturing semiconductor device Apr. 2, 2013
8409975 Method for decreasing polysilicon gate resistance in a carbon co-implantation process Apr. 2, 2013
8373237 Transistor and method of manufacturing the same Feb. 12, 2013
8357576 Method of manufacturing semiconductor device Jan. 22, 2013
8338894 Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch Dec. 25, 2012
8329526 Cap removal in a high-k metal gate electrode structure by using a sacrificial fill material Dec. 11, 2012
8329566 Method of manufacturing a high-performance semiconductor device Dec. 11, 2012
8324043 Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers Dec. 4, 2012
8304318 Methods of fabricating MOS transistors having recesses with elevated source/drain regions Nov. 6, 2012
8299535 Delta monolayer dopants epitaxy for embedded source/drain silicide Oct. 30, 2012
8278718 Stressed barrier plug slot contact structure for transistor performance enhancement Oct. 2, 2012
8268694 Method of manufacturing a transistor and method of manufacturing a semiconductor device Sep. 18, 2012
8236660 Monolayer dopant embedded stressor for advanced CMOS Aug. 7, 2012
8236637 Planar silicide semiconductor structure Aug. 7, 2012
8222701 P-channel MOS transistor and semiconductor integrated circuit device Jul. 17, 2012
8211761 Semiconductor system using germanium condensation Jul. 3, 2012
8212253 Shallow junction formation and high dopant activation rate of MOS devices Jul. 3, 2012
8211784 Method for manufacturing a semiconductor device with less leakage current induced by carbon implant Jul. 3, 2012
8198165 Method for manufacturing semiconductor device Jun. 12, 2012
8193065 Asymmetric source and drain stressor regions Jun. 5, 2012
8187975 Hydrochloric acid etch and low temperature epitaxy in a single chamber for raised source-drain fabrication May. 29, 2012

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