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Class Information
Number: 257/E21.634
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Complementary field-effect transistors, e.g., cmos (epo) > With particular manufacturing method of source or drain, e.g., specific s or d implants or silicided s or d structures or raised s or d structures (epo)
Description: This subclass is indented under subclass E21.632. This subclass is substantially the same in scope as ECLA classification H01L21/8238D.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7618856 |
Method for fabricating strained-silicon CMOS transistors |
Nov. 17, 2009 |
| 7595247 |
Halo-first ultra-thin SOI FET for superior short channel control |
Sep. 29, 2009 |
| 7592619 |
Epitaxy layer and method of forming the same |
Sep. 22, 2009 |
| 7592684 |
Semiconductor device and method for manufacturing the same |
Sep. 22, 2009 |
| 7585739 |
Semiconductor device and method of fabricating the same |
Sep. 8, 2009 |
| 7585735 |
Asymmetric spacers and asymmetric source/drain extension layers |
Sep. 8, 2009 |
| 7579248 |
Resolving pattern-loading issues of SiGe stressor |
Aug. 25, 2009 |
| 7569457 |
Method of fabricating semiconductor device |
Aug. 4, 2009 |
| 7557000 |
Etching method and structure using a hard mask for strained silicon MOS transistors |
Jul. 7, 2009 |
| 7556954 |
MOS transistor and manufacturing method thereof |
Jul. 7, 2009 |
| 7553718 |
Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps |
Jun. 30, 2009 |
| 7550336 |
Method for fabricating an NMOS transistor |
Jun. 23, 2009 |
| 7547595 |
Integration scheme method and structure for transistors using strained silicon |
Jun. 16, 2009 |
| 7534677 |
Method of fabricating a dual gate oxide |
May. 19, 2009 |
| 7528067 |
MOSFET structure with multiple self-aligned silicide contacts |
May. 5, 2009 |
| 7521326 |
Semiconductor device and manufacturing method thereof |
Apr. 21, 2009 |
| 7479422 |
Semiconductor device with stressors and method therefor |
Jan. 20, 2009 |
| 7468313 |
Engineering strain in thick strained-SOI substrates |
Dec. 23, 2008 |
| 7462537 |
Fabricating method of an non-volatile memory |
Dec. 9, 2008 |
| 7456068 |
Forming ultra-shallow junctions |
Nov. 25, 2008 |
| 7453120 |
Semiconductor structure |
Nov. 18, 2008 |
| 7432146 |
Semiconductor device and manufacturing method thereof |
Oct. 7, 2008 |
| 7432167 |
Method of fabricating a strained silicon channel metal oxide semiconductor transistor |
Oct. 7, 2008 |
| 7432136 |
Transistors with controllable threshold voltages, and various methods of making and operating same |
Oct. 7, 2008 |
| 7416931 |
Methods for fabricating a stress enhanced MOS circuit |
Aug. 26, 2008 |
| 7413946 |
Formation of standard voltage threshold and low voltage threshold MOSFET devices |
Aug. 19, 2008 |
| 7414277 |
Memory cell having combination raised source and drain and method of fabricating same |
Aug. 19, 2008 |
| 7410876 |
Methodology to reduce SOI floating-body effect |
Aug. 12, 2008 |
| 7410875 |
Semiconductor structure and fabrication thereof |
Aug. 12, 2008 |
| 7402484 |
Methods for forming a field effect transistor |
Jul. 22, 2008 |
| 7402479 |
CMOS image sensor and fabricating method thereof |
Jul. 22, 2008 |
| 7390711 |
MOS transistor and manufacturing method thereof |
Jun. 24, 2008 |
| 7381623 |
Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance |
Jun. 3, 2008 |
| 7365010 |
Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same |
Apr. 29, 2008 |
| 7348233 |
Methods for fabricating a CMOS device including silicide contacts |
Mar. 25, 2008 |
| 7348248 |
CMOS transistor with high drive current and low sheet resistance |
Mar. 25, 2008 |
| 7344984 |
Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors |
Mar. 18, 2008 |
| 7329570 |
Method for manufacturing a semiconductor device |
Feb. 12, 2008 |
| 7326622 |
Method of manufacturing semiconductor MOS transistor device |
Feb. 5, 2008 |
| 7319061 |
Method for fabricating electronic device |
Jan. 15, 2008 |
| 7314789 |
Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification |
Jan. 1, 2008 |
| 7300832 |
Semiconductor manufacturing method using two-stage annealing |
Nov. 27, 2007 |
| 7282402 |
Method of making a dual strained channel semiconductor device |
Oct. 16, 2007 |
| 7282416 |
Method for fabricating electronic device |
Oct. 16, 2007 |
| 7279406 |
Tailoring channel strain profile by recessed material composition control |
Oct. 9, 2007 |
| 7259054 |
Method of manufacturing a semiconductor device that includes a process for forming a high breakdown voltage field effect transistor |
Aug. 21, 2007 |
| 7259056 |
Method for manufacturing semiconductor device |
Aug. 21, 2007 |
| 7253060 |
Gate-all-around type of semiconductor device and method of fabricating the same |
Aug. 7, 2007 |
| 7253039 |
Method of manufacturing CMOS transistor by using SOI substrate |
Aug. 7, 2007 |
| 7247535 |
Source/drain extensions having highly activated and extremely abrupt junctions |
Jul. 24, 2007 |
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