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Class Information
Number: 257/E21.632
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Complementary field-effect transistors, e.g., cmos (epo)
Description: This subclass is indented under subclass E21.616. This subclass is substantially the same in scope as ECLA classification H01L21/8238.

Sub-classes under this class:

Class Number Class Name Patents
257/E21.641 Interconnection or wiring or contact manufacturing related aspects (epo) 266
257/E21.642 Isolation region manufacturing related aspects, e.g., to avoid interaction of isolation region with adjacent structure (epo) 357
257/E21.633 With particular manufacturing method of channel, e.g., channel implants, halo or pocket implants, or channel materials (epo) 602
257/E21.635 With particular manufacturing method of gate conductor, e.g., particular materials, shapes (epo) 187
257/E21.639 With particular manufacturing method of gate insulating layer, e.g., different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants (epo) 372
257/E21.64 With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (epo) 368
257/E21.634 With particular manufacturing method of source or drain, e.g., specific s or d implants or silicided s or d structures or raised s or d structures (epo) 699
257/E21.643 With particular manufacturing method of vertical transistor structures, i.e., with channel vertical to substrate surface (epo) 94

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Patent Number Title Of Patent Date Issued
8709929 Methods of forming semiconductor devices having diffusion regions of reduced width Apr. 29, 2014
8691642 Method of fabricating semiconductor device including forming epitaxial blocking layers by nitridation process Apr. 8, 2014
8679950 Manufacturing method for semiconductor device having side by side different fins Mar. 25, 2014
8674448 Trigate static random-access memory with independent source and drain engineering, and devices made therefrom Mar. 18, 2014
8673699 Semiconductor structure having NFET extension last implants Mar. 18, 2014
8674402 Power semiconductor device and methods for fabricating the same Mar. 18, 2014
8669153 Integrating a first contact structure in a gate last process Mar. 11, 2014
8664058 Semiconductor device having silicon on stressed liner (SOL) Mar. 4, 2014
8643115 Structure and method of T.sub.inv scaling for high .kappa. metal gate technology Feb. 4, 2014
8642435 Performing treatment on stressors Feb. 4, 2014
8642417 Method of manufacturing strained source/drain structures Feb. 4, 2014
8642407 Devices having reduced susceptibility to soft-error effects and method for fabrication Feb. 4, 2014
8629014 Replacement metal gate structures for effective work function control Jan. 14, 2014
8617947 Method of manufacturing semiconductor device Dec. 31, 2013
8609479 Gated-varactors Dec. 17, 2013
8609482 Enhancing interface characteristics between a channel semiconductor alloy and a gate dielectric by an oxidation process Dec. 17, 2013
8609518 Re-growing source/drain regions from un-relaxed silicon layer Dec. 17, 2013
8604557 Semiconductor memory device and method for manufacturing Dec. 10, 2013
8604553 Semiconductor device and manufacturing method thereof Dec. 10, 2013
8604529 Apparatus with photodiode region in multiple epitaxial layers Dec. 10, 2013
8603887 Method for depositing a silicon oxide layer of same thickness on silicon and on silicon-germanium Dec. 10, 2013
8597993 Electrostatic discharge (ESD) device and method of fabricating Dec. 3, 2013
8592922 Transistor device and a method of manufacturing the same Nov. 26, 2013
8586475 Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same Nov. 19, 2013
8580624 Nanowire FET and finFET hybrid technology Nov. 12, 2013
8580630 Methods for forming a metal gate structure on a substrate Nov. 12, 2013
8574979 Method for integrating silicon germanium and carbon doped silicon with source/drain regions in a strained CMOS process flow Nov. 5, 2013
8575705 Semiconductor devices including MOS transistors having an optimized channel region and methods of fabricating the same Nov. 5, 2013
8569137 Method of improving PMOS performance in a contact etch stop layer process Oct. 29, 2013
8557649 Method for controlling structure height Oct. 15, 2013
8551833 Double gate planar field effect transistors Oct. 8, 2013
8552507 Semiconductor device and method of manufacturing the same Oct. 8, 2013
8546203 Semiconductor structure having NFET extension last implants Oct. 1, 2013
8535998 Method for fabricating a gate structure Sep. 17, 2013
8535999 Stress memorization process improvement for improved technology performance Sep. 17, 2013
8536654 Structure and method for dual work function metal gate CMOS with selective capping Sep. 17, 2013
8530286 Low power semiconductor transistor structure and method of fabrication thereof Sep. 10, 2013
8530296 High voltage transistor using diluted drain Sep. 10, 2013
8530295 Floating body cell structures, devices including same, and methods for forming same Sep. 10, 2013
8530294 Stress modulation for metal gate semiconductor device Sep. 10, 2013
8519402 Structure, structure and method of latch-up immunity for high and low voltage integrated circuits Aug. 27, 2013
8513105 Flexible integration of logic blocks with transistors of different threshold voltages Aug. 20, 2013
8501567 Manufacturing method of high voltage device Aug. 6, 2013
8502320 Zener diode structure and process Aug. 6, 2013
8497212 Filling narrow openings using ion beam etch Jul. 30, 2013
8497542 ZrXHfYSn1-X-YO2 films as high K gate dielectrics Jul. 30, 2013
8492849 High side semiconductor structure Jul. 23, 2013
8492844 Fully depleted SOI device with buried doped layer Jul. 23, 2013
8492768 Semiconductor device and method of fabricating the same Jul. 23, 2013
8492218 Removal of an overlap of dual stress liners Jul. 23, 2013

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

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