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Class Information
Number: 257/E21.631
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > Combination of enhancement and depletion transistors (epo)
Description: This subclass is indented under subclass E21.616. This subclass is substantially the same in scope as ECLA classification H01L21/8236.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8673731 Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices Mar. 18, 2014
8669167 Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices Mar. 11, 2014
8669615 Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices Mar. 11, 2014
8659084 Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices Feb. 25, 2014
8502323 Reliable normally-off III-nitride active device structures, and related methods and systems Aug. 6, 2013
8486786 Enhancing uniformity of a channel semiconductor alloy by forming STI structures after the growth process Jul. 16, 2013
8487375 Semiconductor device and method of manufacturing semiconductor device Jul. 16, 2013
8293606 Body tie test structure for accurate body effect measurement Oct. 23, 2012
8173510 Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric May. 8, 2012
8148226 Method of fabricating semiconductor device Apr. 3, 2012
8143130 Method of manufacturing depletion MOS device Mar. 27, 2012
8138038 Superior fill conditions in a replacement gate approach by performing a polishing process based on a sacrificial fill material Mar. 20, 2012
8035139 Dynamic random access memory having junction field effect transistor cell access device Oct. 11, 2011
7888732 Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric Feb. 15, 2011
7880229 Body tie test structure for accurate body effect measurement Feb. 1, 2011
7833819 Method and apparatus for decreasing storage node parasitic charge in active pixel image sensors Nov. 16, 2010
7829957 Semiconductor device and manufacturing method thereof Nov. 9, 2010
7772647 Structure and design structure having isolated back gates for fully depleted SOI devices Aug. 10, 2010
7718500 Formation of raised source/drain structures in NFET with embedded SiGe in PFET May. 18, 2010
7659157 Dual metal gate finFETs with single or dual high-K gate dielectric Feb. 9, 2010
7449728 Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same Nov. 11, 2008
7288463 Pulsed deposition layer gap fill with expansion material Oct. 30, 2007
7282402 Method of making a dual strained channel semiconductor device Oct. 16, 2007
7265421 Insulated-gate field-effect thin film transistors Sep. 4, 2007
7087967 LSI device having core and interface regions with SOI layers of different thickness Aug. 8, 2006
6740561 Method of manufacturing a semiconductor device May. 25, 2004
6448121 High threshold PMOS transistor in a surface-channel process Sep. 10, 2002
6054354 High voltage field effect transistors with selective gate depletion Apr. 25, 2000
5976938 Method of making enhancement-mode and depletion-mode IGFETs with different gate thicknesses Nov. 2, 1999
5969392 Thermal ink jet printheads with power MOS driver devices having enhanced transconductance Oct. 19, 1999
5885874 Method of making enhancement-mode and depletion-mode IGFETS using selective doping of a gate material Mar. 23, 1999
5514610 Method of making an optimized code ion implantation procedure for read only memory devices May. 7, 1996
5266515 Fabricating dual gate thin film transistors Nov. 30, 1993
5257095 Common geometry high voltage tolerant long channel and high speed short channel field effect transistors Oct. 26, 1993
5229633 High voltage lateral enhancement IGFET Jul. 20, 1993
5139962 MOS fabrication method with self-aligned gate Aug. 18, 1992
5135880 Method of manufacturing a semiconductor device Aug. 4, 1992
5075250 Method of fabricating a monolithic integrated circuit chip for a thermal ink jet printhead Dec. 24, 1991
4892836 Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices Jan. 9, 1990
4849368 Method of producing a two-dimensional electron gas semiconductor device Jul. 18, 1989
4742379 HEMT with etch-stop May. 3, 1988
4721686 Manufacturing integrated circuits containing P-channel MOS transistors and bipolar transistors utilizing boron and arsenic as dopants Jan. 26, 1988
4679303 Method of fabricating high density MOSFETs with field aligned channel stops Jul. 14, 1987
4649638 Construction of short-length electrode in semiconductor device Mar. 17, 1987
4600933 Semiconductor integrated circuit structure with selectively modified insulation layer Jul. 15, 1986
4503601 Oxide trench structure for polysilicon gates and interconnects Mar. 12, 1985
4481704 Method of making an improved MESFET semiconductor device Nov. 13, 1984
4315781 Method of controlling MOSFET threshold voltage with self-aligned channel stop Feb. 16, 1982
4246044 Method for fabricating semi-conductor devices Jan. 20, 1981
4229755 Fabrication of very large scale integrated circuits containing N-channel silicon gate nonvolatile memory elements Oct. 21, 1980

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