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Class Information
Number: 257/E21.63
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > With particular manufacturing method of wells or tubs, e.g., twin tubs, high energy well implants, buried implanted layers for lateral isolation (billi) (epo)
Description: This subclass is indented under subclass E21.616. This subclass is substantially the same in scope as ECLA classification H01L21/8234W.

Sub-classes under this class:

Class Number Class Name Patents

Patents under this class:
1 2 3

Patent Number Title Of Patent Date Issued
8614128 CMOS structures and processes based on selective thinning Dec. 24, 2013
8519402 Structure, structure and method of latch-up immunity for high and low voltage integrated circuits Aug. 27, 2013
8455338 Method of forming a semiconductor device introducing plural impurities to form plural wells Jun. 4, 2013
8320165 SRAM strap row substrate contact Nov. 27, 2012
8315086 SRAM strap row well contact Nov. 20, 2012
8310860 SRAM strap row double well contact Nov. 13, 2012
8198150 Method of forming a semiconductor die with aluminum-spiked heat pipes Jun. 12, 2012
8125041 Semiconductor device Feb. 28, 2012
8039326 Methods for fabricating bulk FinFET devices having deep trench isolation Oct. 18, 2011
RE42776 Tap connections for circuits with leakage suppression capability Oct. 4, 2011
7977200 Charge breakdown avoidance for MIM elements in SOI base technology and method Jul. 12, 2011
7964894 Integrated circuit system employing stress memorization transfer Jun. 21, 2011
7943461 High-voltage semiconductor device and method for manufacturing the same May. 17, 2011
7915688 Semiconductor device with MISFET Mar. 29, 2011
7906389 Butted source contact and well strap Mar. 15, 2011
7855116 Nonvolatile semiconductor memory device and manufacturing method thereof Dec. 21, 2010
7776643 Solid state image pickup device and its manufacture method Aug. 17, 2010
7772647 Structure and design structure having isolated back gates for fully depleted SOI devices Aug. 10, 2010
7755146 Formation of standard voltage threshold and low voltage threshold MOSFET devices Jul. 13, 2010
7736957 Method of making a semiconductor device with embedded stressor Jun. 15, 2010
7714358 Semiconductor structure and method of forming the structure May. 11, 2010
7700470 Selective anisotropic wet etching of workfunction metal for semiconductor devices Apr. 20, 2010
7696579 Formation of standard voltage threshold and low voltage threshold MOSFET devices Apr. 13, 2010
7691734 Deep trench based far subcollector reachthrough Apr. 6, 2010
7691701 Method of forming gate stack and structure thereof Apr. 6, 2010
7687363 Method for manufacturing semiconductor device Mar. 30, 2010
7682918 ESD protection for semiconductor products Mar. 23, 2010
7659157 Dual metal gate finFETs with single or dual high-K gate dielectric Feb. 9, 2010
7645658 Method of manufacturing silicon carbide semiconductor device Jan. 12, 2010
7632724 Stressed SOI FET having tensile and compressive device regions Dec. 15, 2009
7612422 Structure for dual work function metal gate electrodes by control of interface dipoles Nov. 3, 2009
7608501 Technique for creating different mechanical strain by forming a contact etch stop layer stack having differently modified intrinsic stress Oct. 27, 2009
7605412 Distributed high voltage JFET Oct. 20, 2009
7569446 Semiconductor structure and method of manufacture Aug. 4, 2009
7556990 CMOS image sensor having improved signal efficiency and method for manufacturing the same Jul. 7, 2009
7544560 Image sensor and fabrication method thereof Jun. 9, 2009
7537988 Differential offset spacer May. 26, 2009
7521312 Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device Apr. 21, 2009
7504289 Process for forming an electronic device including transistor structures with sidewall spacers Mar. 17, 2009
7482217 Forming metal-semiconductor films having different thicknesses within different regions of an electronic device Jan. 27, 2009
7482219 Technique for creating different mechanical strain by a contact etch stop layer stack with an intermediate etch stop layer Jan. 27, 2009
7439123 Low resistance contact semiconductor device structure Oct. 21, 2008
7419893 Method of manufacturing semiconductor device having triple-well structure and semiconductor device fabricated Sep. 2, 2008
7351628 Atomic layer deposition of CMOS gates with variable work functions Apr. 1, 2008
7335549 Semiconductor device and method for fabricating the same Feb. 26, 2008
7309661 Method for forming gate of semiconductor device Dec. 18, 2007
7285453 Triple well structure and method for manufacturing the same Oct. 23, 2007
7282402 Method of making a dual strained channel semiconductor device Oct. 16, 2007
7273776 Methods of forming a P-well in an integrated circuit device Sep. 25, 2007
7211481 Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer May. 1, 2007

1 2 3

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