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Class Information
Number: 257/E21.626
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (epo)
Description: This subclass is indented under subclass E21.616. This subclass is substantially the same in scope as ECLA classification H01L21/8234S.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8680602 Semiconductor device and method of manufacturing the same Mar. 25, 2014
8673725 Multilayer sidewall spacer for seam protection of a patterned structure Mar. 18, 2014
8664709 Non-volatile memory and fabricating method thereof Mar. 4, 2014
8664102 Dual sidewall spacer for seam protection of a patterned structure Mar. 4, 2014
8614469 Semiconductor device and manufacturing method of the same Dec. 24, 2013
8603882 Method for making dual silicide and germanide semiconductors Dec. 10, 2013
8598005 Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices Dec. 3, 2013
8569168 Dual-metal self-aligned wires and vias Oct. 29, 2013
8551849 Semiconductor device and method of manufacturing the same Oct. 8, 2013
8530315 finFET with fully silicided gate Sep. 10, 2013
8502325 Metal high-K transistor having silicon sidewalls for reduced parasitic capacitance Aug. 6, 2013
8492227 Method of forming side wall spacers for a semiconductor device Jul. 23, 2013
8486778 Low resistance source and drain extensions for ETSOI Jul. 16, 2013
8476680 Semiconductor device and method for manufacturing the same Jul. 2, 2013
8466023 Semiconductor device and method for fabricating the same Jun. 18, 2013
8461049 Method for fabricating semiconductor device Jun. 11, 2013
8440534 Threshold adjustment for MOS devices by adapting a spacer width prior to implantation May. 14, 2013
8431461 Silicon nitride dry trim without top pulldown Apr. 30, 2013
8426266 Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devices Apr. 23, 2013
8421166 Semiconductor device and fabrication thereof Apr. 16, 2013
8389371 Method of fabricating integrated circuit device, including removing at least a portion of a spacer Mar. 5, 2013
8384165 Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow Feb. 26, 2013
8324110 Field effect transistor (FET) and method of forming the FET without damaging the wafer surface Dec. 4, 2012
8324107 Method for forming high density patterns Dec. 4, 2012
8309414 Semiconductor device and method of manufacturing semiconductor device Nov. 13, 2012
8304834 Semiconductor local interconnect and contact Nov. 6, 2012
8299508 CMOS structure with multiple spacers Oct. 30, 2012
8294186 Semiconductor device and manufacturing method of the same Oct. 23, 2012
8278168 Methods of forming a semiconductor device Oct. 2, 2012
8278721 Contact hole, semiconductor device and method for forming the same Oct. 2, 2012
8258588 Sealing layer of a field effect transistor Sep. 4, 2012
8252675 Methods of forming CMOS transistors with high conductivity gate electrodes Aug. 28, 2012
8253204 Semiconductor device with strained channel and method of fabricating the same Aug. 28, 2012
8252676 Method for containing a silicided gate within a sidewall spacer in integrated circuit technology Aug. 28, 2012
8237205 Semiconductor device and method for fabricating the same Aug. 7, 2012
8216908 Extended drain transistor and method of manufacturing the same Jul. 10, 2012
8211777 Method of manufacturing nonvolatile semiconductor device Jul. 3, 2012
8202782 Method of manufacturing transistor Jun. 19, 2012
8187961 Threshold adjustment for high-K gate dielectric CMOS May. 29, 2012
8187962 Self aligned silicided contacts May. 29, 2012
8154088 Semiconductor topography and method for reducing gate induced drain leakage (GIDL) in MOS transistors Apr. 10, 2012
8134189 Semiconductor device and method of manufacturing the same Mar. 13, 2012
8133777 Method of fabricating memory Mar. 13, 2012
8119470 Mitigation of gate to contact capacitance in CMOS flow Feb. 21, 2012
8067284 Oxynitride bilayer formed using a precursor inducing a high charge trap density in a top layer of the bilayer Nov. 29, 2011
8048752 Spacer shape engineering for void-free gap-filling process Nov. 1, 2011
8043915 Pitch multiplied mask patterns for isolated features Oct. 25, 2011
8039381 Photoresist etch back method for gate last process Oct. 18, 2011
8008204 Method of manufacturing semiconductor device Aug. 30, 2011
8003460 Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure Aug. 23, 2011

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