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Class Information
Number: 257/E21.619
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Field-effect technology (epo) > Mis technology (epo) > With particular manufacturing method of source or drain, e.g., specific s or d implants or silicided s or d structures or raised s or d structures (epo)
Description: This subclass is indented under subclass E21.616. This subclass is substantially the same in scope as ECLA classification H01L21/8234D.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.62 Manufacturing common source or drain regions between plurality of conductor-insulator-semiconductor structures (epo) 207


Patents under this class:
1 2 3 4 5 6 7 8

Patent Number Title Of Patent Date Issued
8692335 Source/drain region, contact hole and method for forming the same Apr. 8, 2014
8679928 Methods for stressing transistor channels of a semiconductor device structure Mar. 25, 2014
8664068 Low-diffusion drain and source regions in CMOS transistors for low power/high performance applications Mar. 4, 2014
8658460 Organic light-emitting display device and method of manufacturing the same Feb. 25, 2014
8658504 Method for manufacturing semiconductor device Feb. 25, 2014
8652915 Methods of fabricating semiconductor devices using preliminary trenches with epitaxial growth Feb. 18, 2014
8642435 Performing treatment on stressors Feb. 4, 2014
8642434 Structure and method for mobility enhanced MOSFETS with unalloyed silicide Feb. 4, 2014
8642431 N-type carrier enhancement in semiconductors Feb. 4, 2014
8642417 Method of manufacturing strained source/drain structures Feb. 4, 2014
8623721 Silicide formation and associated devices Jan. 7, 2014
8614132 Integrated circuit device with well controlled surface proximity and method of manufacturing same Dec. 24, 2013
8610233 Hybrid MOSFET structure having drain side schottky junction Dec. 17, 2013
8609499 FinFETs and the methods for forming the same Dec. 17, 2013
8598024 Fabricating method of metal silicide layer, fabricating method of semiconductor device using the same and semiconductor device fabricated using the method Dec. 3, 2013
8598656 Method and apparatus of forming ESD protection device Dec. 3, 2013
8574970 Method of forming an extremely thin semiconductor insulator (ETSOI) FET having a stair-shaped raised source/drain Nov. 5, 2013
8546221 Voltage converter and systems including same Oct. 1, 2013
8546228 Strained thin body CMOS device having vertically raised source/drain stressors with single spacer Oct. 1, 2013
8536619 Strained MOS device and methods for forming the same Sep. 17, 2013
8536011 Junction leakage suppression in memory devices Sep. 17, 2013
8530315 finFET with fully silicided gate Sep. 10, 2013
8524566 Methods for the fabrication of integrated circuits including back-etching of raised conductive structures Sep. 3, 2013
8518782 Semiconductor device including asymmetric lightly doped drain (LDD) region, related method and design structure Aug. 27, 2013
8513727 Surrounding stacked gate multi-gate FET structure nonvolatile memory device Aug. 20, 2013
8513738 ESD field-effect transistor and integrated diffusion resistor Aug. 20, 2013
8497179 Method of fabricating multi-fingered semiconductor devices on a common substrate Jul. 30, 2013
8470666 Methods of making random access memory devices, transistors, and memory cells Jun. 25, 2013
8470707 Silicide method Jun. 25, 2013
8460981 Use of contacts to create differential stresses on devices Jun. 11, 2013
8455930 Strained semiconductor device with facets Jun. 4, 2013
8450814 Extended drain lateral DMOS transistor with reduced gate charge and self-aligned extended drain May. 28, 2013
8435855 Methods of manufacturing semiconductor devices May. 7, 2013
8435848 PMOS SiGe-last integration process May. 7, 2013
8435846 Semiconductor devices with raised extensions May. 7, 2013
8420471 Dense pitch bulk FinFET process by selective EPI and etch Apr. 16, 2013
8421159 Raised source/drain field effect transistor Apr. 16, 2013
8405088 Thin film transistor and organic light emitting diode display device Mar. 26, 2013
8404538 Device with self aligned stressor and method of making same Mar. 26, 2013
8394712 Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions Mar. 12, 2013
8377787 Alternating-doping profile for source/drain of a FET Feb. 19, 2013
8373237 Transistor and method of manufacturing the same Feb. 12, 2013
8368151 Semiconductor device Feb. 5, 2013
8362526 Liquid crystal display device and fabricating method thereof Jan. 29, 2013
8362546 Cross-point diode arrays and methods of manufacturing cross-point diode arrays Jan. 29, 2013
8362555 Voltage converter and systems including same Jan. 29, 2013
8354316 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection Jan. 15, 2013
8334573 Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices Dec. 18, 2012
8324058 Contacts for FET devices Dec. 4, 2012
8324059 Method of fabricating a semiconductor structure Dec. 4, 2012

1 2 3 4 5 6 7 8










 
 
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