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Class Information
Number: 257/E21.61
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo) > Bipolar technology (epo) > Comprising merged transistor logic or integrated injection logic (epo)
Description: This subclass is indented under subclass E21.608. This subclass is substantially the same in scope as ECLA classification H01L21/8226.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8609496 Method of fabricating semiconductor device comprising a dummy well Dec. 17, 2013
8536006 Logic and non-volatile memory (NVM) integration Sep. 17, 2013
8080440 Resistor random access memory cell with L-shaped electrode Dec. 20, 2011
7977186 Providing local boosting control implant for non-volatile memory Jul. 12, 2011
7847374 Non-volatile memory cell array and logic Dec. 7, 2010
7804134 MOSFET on SOI device Sep. 28, 2010
7732246 Method for fabricating vertical CMOS image sensor Jun. 8, 2010
7732800 Resistor random access memory cell with L-shaped electrode Jun. 8, 2010
7524710 Radiation-hardened silicon-on-insulator CMOS device, and method of making the same Apr. 28, 2009
7456069 Method in the fabrication of an integrated injection logic circuit Nov. 25, 2008
7220648 Methods of forming integrated circuit devices including raised source/drain structures having different heights May. 22, 2007
6573146 Methods of manufacturing complementary bipolar transistors Jun. 3, 2003
6326674 Integrated injection logic devices including injection regions and tub or sink regions Dec. 4, 2001
6232193 Method of forming isolated integrated injection logic gate May. 15, 2001
6140694 Field isolated integrated injection logic gate Oct. 31, 2000
6005284 Semiconductor device and its manufacturing method Dec. 21, 1999
6005283 Complementary bipolar transistors Dec. 21, 1999
5331198 Semiconductor device including IIL and vertical transistors Jul. 19, 1994
5323054 Semiconductor device including integrated injection logic and vertical NPN and PNP transistors Jun. 21, 1994
5280188 Method of manufacturing a semiconductor integrated circuit device having at least one bipolar transistor and a plurality of MOS transistors Jan. 18, 1994
5162252 Method of fabricating IIL and vertical complementary bipolar transistors Nov. 10, 1992
5153697 Integrated circuit that combines multi-epitaxial power transistors with logic/analog devices, and a process to produce same Oct. 6, 1992
5144408 Semiconductor integrated circuit device and method of manufacturing the same Sep. 1, 1992
5034337 Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices Jul. 23, 1991
5023687 Semiconductor device Jun. 11, 1991
4935800 Semiconductor integrated circuit Jun. 19, 1990
4745085 Method of making I.sup.2 L heterostructure bipolar transistors May. 17, 1988
4694321 Semiconductor device having bipolar transistor and integrated injection logic Sep. 15, 1987
4656498 Oxide-isolated integrated Schottky logic Apr. 7, 1987
4644381 I.sup.2 L heterostructure bipolar transistors and method of making the same Feb. 17, 1987
4599635 Semiconductor integrated circuit device and method of producing same Jul. 8, 1986
4567501 Resistor structure in integrated injection logic Jan. 28, 1986
4546539 I.sup.2 L Structure and fabrication process compatible with high voltage bipolar transistors Oct. 15, 1985
4404737 Method for manufacturing a semiconductor integrated circuit utilizing polycrystalline silicon deposition, oxidation and etching Sep. 20, 1983
4390890 Saturation-limited bipolar transistor device Jun. 28, 1983
4377903 Method for manufacturing an I.sup.2 L semiconductor device Mar. 29, 1983
4338139 Method of forming Schottky-I.sup.2 L devices by implantation and laser bombardment Jul. 6, 1982
4322882 Method for making an integrated injection logic structure including a self-aligned base contact Apr. 6, 1982
4322883 Self-aligned metal process for integrated injection logic integrated circuits Apr. 6, 1982
4272307 Integrated circuit with I.sup.2 L and power transistors and method for making Jun. 9, 1981
4260430 Method of manufacturing a semiconductor device Apr. 7, 1981
4258379 IIL With in and outdiffused emitter pocket Mar. 24, 1981
4255209 Process of fabricating an improved I.sup.2 L integrated circuit utilizing diffusion and epitaxial deposition Mar. 10, 1981
4228448 Bipolar integrated semiconductor structure including I.sup.2 L and linear type devices and fabrication methods therefor Oct. 14, 1980
4210925 I.sup.2 L Integrated circuit and process of fabrication Jul. 1, 1980
4201800 Hardened photoresist master image mask process May. 6, 1980
4199378 Method of manufacturing a semiconductor device and semiconductor device manufactured while using such a method Apr. 22, 1980
4197147 Method of manufacturing an integrated circuit including an analog circuit and an I.sup.2 L circuit utilizing staged diffusion techniques Apr. 8, 1980
4168999 Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques Sep. 25, 1979
4160988 Integrated injection logic (I-squared L) with double-diffused type injector Jul. 10, 1979

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