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Class Information
Number: 257/E21.606
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (epo) > With subsequent division of substrate into plural individual devices (epo) > To produce devices each consisting of plurality of components, e.g., integrated circuits (epo) > Substrate being semiconductor, using silicon technology (epo)
Description: This subclass is indented under subclass E21.602. This subclass is substantially the same in scope as ECLA classification H01L21/822.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.608 Bipolar technology (epo) 202
257/E21.614 Three-dimensional integrated circuits stacked in different levels (epo) 438
257/E21.615 Field-effect technology (epo) 44
257/E21.695 Combination of bipolar and field-effect technologies (epo) 58


Patents under this class:
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Patent Number Title Of Patent Date Issued
8610236 Edge devices layout for improved performance Dec. 17, 2013
8492176 Method of manufacturing semiconductor device Jul. 23, 2013
8163616 Methods of manufacturing nonvolatile memory devices Apr. 24, 2012
8053829 Methods of fabricating nonvolatile memory devices Nov. 8, 2011
8039313 Method for producing a semiconductor device including connecting a functional wafer to a carrier substrate and selectively etching the carrier substrate Oct. 18, 2011
8017453 Method and apparatus for forming an integrated circuit electrode having a reduced contact area Sep. 13, 2011
8003546 Method of growing silicon and method of manufacturing solar cell using the same Aug. 23, 2011
7906363 Method of fabricating semiconductor device having three-dimensional stacked structure Mar. 15, 2011
7759201 Method for fabricating pitch-doubling pillar structures Jul. 20, 2010
7727812 Singulation method of semiconductor device Jun. 1, 2010
7723141 Encapsulation in a hermetic cavity of a microelectronic composite, particularly of a MEMS May. 25, 2010
7514276 Aligning stacked chips using resistance assistance Apr. 7, 2009
7399683 Manufacturing method of semiconductor device Jul. 15, 2008
7361524 Method of manufacturing floating structure Apr. 22, 2008
7358155 Scribe-line structures and methods of forming the same Apr. 15, 2008
7169682 Method for manufacturing semiconductor device Jan. 30, 2007
7078320 Partial wafer bonding and dicing Jul. 18, 2006
7061062 Integrated circuit with unified input device, microprocessor and display systems Jun. 13, 2006
7059041 Methods for producing passive components on a semiconductor substrate Jun. 13, 2006
6828651 Integrated structure Dec. 7, 2004
6780775 Design of lithography alignment and overlay measurement marks on CMP finished damascene surface Aug. 24, 2004
6465893 Stacked chip assembly Oct. 15, 2002
6433419 Face-up semiconductor chip assemblies Aug. 13, 2002
6417043 Memory cell configuration and fabrication method Jul. 9, 2002
6392306 Semiconductor chip assembly with anisotropic conductive adhesive connections May. 21, 2002
6372527 Methods of making semiconductor chip assemblies Apr. 16, 2002
6291836 Method of operating a programmable, non-volatile memory device Sep. 18, 2001
6114729 Plural wells structure in a semiconductor device Sep. 5, 2000
6107666 High density ROM and a method of making the same Aug. 22, 2000
6100172 Method for forming a horizontal surface spacer and devices formed thereby Aug. 8, 2000
6071763 Method of fabricating layered integrated circuit Jun. 6, 2000
6011272 Silicided shallow junction formation and structure with high and low breakdown voltages Jan. 4, 2000
5950304 Methods of making semiconductor chip assemblies Sep. 14, 1999
5899714 Fabrication of semiconductor structure having two levels of buried regions May. 4, 1999
5889315 Semiconductor structure having two levels of buried regions Mar. 30, 1999
5880014 Plural wells structure in a semiconductor device and method for forming the same Mar. 9, 1999
5840608 High density ROM and a method of making the same Nov. 24, 1998
5838058 Semiconductor substrate and semiconductor device employing the same Nov. 17, 1998
5714400 Method for forming a memory device by utilizing variations in resistance value Feb. 3, 1998
5705408 Method for forming semiconductor integrated circuit using monolayer epitaxial growth Jan. 6, 1998
5685885 Wafer-scale techniques for fabrication of semiconductor chip assemblies Nov. 11, 1997
5682061 Component for connecting a semiconductor chip to a substrate Oct. 28, 1997
5679977 Semiconductor chip assemblies, methods of making same and components for same Oct. 21, 1997
5621247 Memory device with tungsten and aluminum interconnects Apr. 15, 1997
5605851 Method of forming semiconductor device with a buried junction Feb. 25, 1997
5550090 Method for fabricating a monolithic semiconductor device with integrated surface micromachined structures Aug. 27, 1996
5543344 Method of making programmable read-only memory Aug. 6, 1996
5347159 Semiconductor chip assemblies with face-up mounting and rear-surface connection to substrate Sep. 13, 1994
5346861 Semiconductor chip assemblies and methods of making same Sep. 13, 1994
5258330 Semiconductor chip assemblies with fan-in leads Nov. 2, 1993

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