Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Browse by Category: Main > Physics
Class Information
Number: 257/E21.597
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Formed through semiconductor substrate (epo)
Description: This subclass is indented under subclass E21.575. This subclass is substantially the same in scope as ECLA classification H01L21/768T.










Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13

Patent Number Title Of Patent Date Issued
8710670 Integrated circuit packaging system with coupling features and method of manufacture thereof Apr. 29, 2014
8703609 Through-substrate via for semiconductor device Apr. 22, 2014
8704358 Method for forming an integrated circuit Apr. 22, 2014
8704375 Barrier structures and methods for through substrate vias Apr. 22, 2014
8691690 Contact formation method incorporating preventative etch step reducing interlayer dielectric material flake defects Apr. 8, 2014
8686568 Semiconductor package substrates having layered circuit segments, and related methods Apr. 1, 2014
8686565 Stacked chip assembly having vertical vias Apr. 1, 2014
8679887 Method for manufacturing a micro-electro-mechanical device, in particular an optical microswitch, and micro-electro-mechanical device thus obtained Mar. 25, 2014
8680654 Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods Mar. 25, 2014
8674514 Wiring board, manufacturing method of the wiring board, and semiconductor package Mar. 18, 2014
8673767 Manufacturing method for semiconductor device Mar. 18, 2014
8669179 Through-wafer interconnects for photoimager and memory wafers Mar. 11, 2014
8664772 Interface substrate with interposer Mar. 4, 2014
8664768 Interposer having a defined through via pattern Mar. 4, 2014
8658534 Method for producing a semiconductor component, and semiconductor component Feb. 25, 2014
8648472 Semiconductor device Feb. 11, 2014
8633107 Method of producing a semiconductor device and semiconductor device having a through-wafer interconnect Jan. 21, 2014
8633572 Low ohmic through substrate interconnection for semiconductor carriers Jan. 21, 2014
8629542 Three dimensional structure memory Jan. 14, 2014
8623751 Through-hole electrode substrate and method of manufacturing the same Jan. 7, 2014
8623762 Semiconductor device and a method for making the semiconductor device Jan. 7, 2014
8618651 Buried TSVs used for decaps Dec. 31, 2013
8617989 Liner property improvement Dec. 31, 2013
8617925 Methods of forming bonded semiconductor structures in 3D integration processes using recoverable substrates, and bonded semiconductor structures formed by such methods Dec. 31, 2013
8614145 Through substrate via formation processing using sacrificial material Dec. 24, 2013
8610259 Multi-function and shielded 3D interconnects Dec. 17, 2013
8609538 Methods relating to the fabrication of devices having conductive substrate vias with catch-pad etch-stops Dec. 17, 2013
8592311 Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures Nov. 26, 2013
8592981 Via structure and method thereof Nov. 26, 2013
8586465 Through silicon via dies and packages Nov. 19, 2013
8586983 Semiconductor chip embedded with a test circuit Nov. 19, 2013
8575725 Through-silicon vias for semicondcutor substrate and method of manufacture Nov. 5, 2013
8563403 Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last Oct. 22, 2013
8557700 Method for manufacturing a chip-size double side connection package Oct. 15, 2013
8552548 Conductive pad on protruding through electrode semiconductor device Oct. 8, 2013
8546255 Method for forming vias in a semiconductor substrate and a semiconductor device having the semiconductor substrate Oct. 1, 2013
8519515 TSV structure and method for forming the same Aug. 27, 2013
8519514 Semiconductor device and manufacturing method thereof Aug. 27, 2013
8518796 Semiconductor die connection system and method Aug. 27, 2013
8518787 Through wafer vias and method of making same Aug. 27, 2013
8518823 Through silicon via and method of forming the same Aug. 27, 2013
8492878 Metal-contamination-free through-substrate via structure Jul. 23, 2013
8486829 Semiconductor element having a conductive via and method for making the same and package having a semiconductor element with a conductive via Jul. 16, 2013
8481401 Component having a through-contact Jul. 9, 2013
8466061 Method for forming a through via in a semiconductor element and semiconductor element comprising the same Jun. 18, 2013
8455357 Method of plating through wafer vias in a wafer for 3D packaging Jun. 4, 2013
8455358 Method of manufacturing via hole in a semiconductor device Jun. 4, 2013
8455973 Region divided substrate and semiconductor device Jun. 4, 2013
8446002 Multilayer wiring substrate having a castellation structure May. 21, 2013
8440565 Semiconductor apparatus manufacturing method and semiconductor apparatus May. 14, 2013

1 2 3 4 5 6 7 8 9 10 11 12 13










 
 
  Recently Added Patents
Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
Battery pack with connecting device
Cylindrical LED fixture
Technology for managing traffic via dual homed connections in communication networks
Electronic device, information processing method, and storage medium
Intelligent and automated code deployment
Nucleic acid-based tests for prenatal gender determination
  Randomly Featured Patents
Reduced load working cycle for a four-stroke combustion engine and engines using said cycle
Methods for processing red cell products for long term storage free of microorganisms
Stowable shelf/rack assembly
Pulse width discriminating circuit
Method and apparatus for performing address mapping in virtual file system of storage unit having a plurality of non-volatile data storage media
Process for manufacturing an integrated circuit structure with metal salicide regions and metal salicide exclusion regions
Aqueous oil and water repellent compositions
Door assembly
Apparatus and method for an adjustable column
Sequencing method and bridging system for accessing shared system resources