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Class Information
Number: 257/E21.59
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Local interconnects; local pads (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C10.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6548871 |
Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer |
Apr. 15, 2003 |
| 6544822 |
Method for fabricating MOSFET device |
Apr. 8, 2003 |
| 6544837 |
SOI stacked DRAM logic |
Apr. 8, 2003 |
| 6544876 |
Titanium boride gate electrode and interconnect and methods regarding same |
Apr. 8, 2003 |
| 6544881 |
Stacked local interconnect structure and method of fabricating same |
Apr. 8, 2003 |
| 6544888 |
Advanced contact integration scheme for deep-sub-150 nm devices |
Apr. 8, 2003 |
| 6545358 |
Integrated circuits having plugs in conductive layers therein and related methods |
Apr. 8, 2003 |
| 6541390 |
Method and composition for selectively etching against cobalt silicide |
Apr. 1, 2003 |
| 6541830 |
Titanium boride gate electrode and interconnect |
Apr. 1, 2003 |
| 6537875 |
Semiconductor memory device for reducing damage to interlevel dielectric layer and fabrication method thereof |
Mar. 25, 2003 |
| 6538277 |
Split-gate flash cell |
Mar. 25, 2003 |
| 6534807 |
Local interconnect junction on insulator (JOI) structure |
Mar. 18, 2003 |
| 6534810 |
Semiconductor memory device having capacitor structure formed in proximity to corresponding transistor |
Mar. 18, 2003 |
| 6534813 |
Semiconductor device having a self-aligned contact structure and methods of forming the same |
Mar. 18, 2003 |
| 6535413 |
Method of selectively forming local interconnects using design rules |
Mar. 18, 2003 |
| 6534389 |
Dual level contacts and method for forming |
Mar. 18, 2003 |
| 6534393 |
Method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity |
Mar. 18, 2003 |
| 6534403 |
Method of making a contact and via structure |
Mar. 18, 2003 |
| 6531724 |
Borderless gate structures |
Mar. 11, 2003 |
| 6528365 |
Semiconductor memory device and method for manufacturing the same |
Mar. 4, 2003 |
| 6528416 |
Semiconductor device and method of making utilizing hemispherical grain silicon technology |
Mar. 4, 2003 |
| 6524915 |
Split-gate flash memory and method of manufacturing the same |
Feb. 25, 2003 |
| 6524948 |
Semiconductor device and method for fabricating the same |
Feb. 25, 2003 |
| 6525366 |
Uniform dielectric layer and method to form same |
Feb. 25, 2003 |
| 6525382 |
Semiconductor memory device and method of manufacturing the same |
Feb. 25, 2003 |
| 6525426 |
Subresolution features for a semiconductor device |
Feb. 25, 2003 |
| 6521927 |
Semiconductor device and method for the manufacture thereof |
Feb. 18, 2003 |
| 6522001 |
Local interconnect structures and methods for making the same |
Feb. 18, 2003 |
| 6506645 |
Depletion compensated polysilicon electrodes |
Jan. 14, 2003 |
| 6506647 |
Method for fabricating a semiconductor integrated circuit device |
Jan. 14, 2003 |
| 6506683 |
In-situ process for fabricating a semiconductor device with integral removal of antireflection and etch stop layers |
Jan. 14, 2003 |
| 6503795 |
Method for fabricating a semiconductor device having a storage cell |
Jan. 7, 2003 |
| 6500709 |
Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures |
Dec. 31, 2002 |
| 6500743 |
Method of copper-polysilicon T-gate formation |
Dec. 31, 2002 |
| 6500751 |
Method of forming recessed thin film landing pad structure |
Dec. 31, 2002 |
| 6501113 |
Semiconductor device with capacitor using high dielectric constant film or ferroelectric film |
Dec. 31, 2002 |
| 6501115 |
Semiconductor integrated circuit device and process for manufacturing the same |
Dec. 31, 2002 |
| 6501131 |
Transistors having independently adjustable parameters |
Dec. 31, 2002 |
| 6498088 |
Stacked local interconnect structure and method of fabricating same |
Dec. 24, 2002 |
| 6495408 |
Local interconnection process for preventing dopant cross diffusion in shared gate electrodes |
Dec. 17, 2002 |
| 6489226 |
SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMOR |
Dec. 3, 2002 |
| 6482689 |
Stacked local interconnect structure and method of fabricating same |
Nov. 19, 2002 |
| 6482693 |
Methods of forming diodes |
Nov. 19, 2002 |
| 6482699 |
Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process |
Nov. 19, 2002 |
| 6483141 |
Semiconductor memory device and manufacturing method thereof |
Nov. 19, 2002 |
| 6483144 |
Semiconductor device having self-aligned contact and landing pad structure and method of forming same |
Nov. 19, 2002 |
| 6483153 |
Method to improve LDD corner control with an in-situ film for local interconnect processing |
Nov. 19, 2002 |
| 6479343 |
DRAM cell capacitor and manufacturing method thereof |
Nov. 12, 2002 |
| 6479351 |
Method of fabricating a self-aligned non-volatile memory cell |
Nov. 12, 2002 |
| 6479355 |
Method for forming landing pad |
Nov. 12, 2002 |
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