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Class Information
Number: 257/E21.59
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Local interconnects; local pads (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C10.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6621683 |
Memory cells with improved reliability |
Sep. 16, 2003 |
| 6613621 |
Methods of forming self-aligned contact pads using a damascene gate process |
Sep. 2, 2003 |
| 6613623 |
High fMAX deep submicron MOSFET |
Sep. 2, 2003 |
| 6613645 |
Method of manufacturing semiconductor device with glue layer in opening |
Sep. 2, 2003 |
| 6614098 |
Semiconductor devices and fabrication thereof |
Sep. 2, 2003 |
| 6614643 |
Semiconductor device having a capacitor element |
Sep. 2, 2003 |
| 6610587 |
Method of forming a local interconnect |
Aug. 26, 2003 |
| 6607954 |
Methods of fabricating cylinder-type capacitors for semiconductor devices using a hard mask and a mold layer |
Aug. 19, 2003 |
| 6605533 |
Process for forming low resistance metal silicide local interconnects |
Aug. 12, 2003 |
| 6602773 |
Methods of fabricating semiconductor devices having protected plug contacts and upper interconnections |
Aug. 5, 2003 |
| 6599824 |
System for and method of forming local interconnect using microcontact printing |
Jul. 29, 2003 |
| 6600191 |
Method of fabricating conductive straps to interconnect contacts to corresponding digit lines by employing an angled sidewall implant and semiconductor devices fabricated thereby |
Jul. 29, 2003 |
| 6596579 |
Method of forming analog capacitor dual damascene process |
Jul. 22, 2003 |
| 6596606 |
Semiconductor raised source-drain structure |
Jul. 22, 2003 |
| 6596623 |
Use of organic spin on materials as a stop-layer for local interconnect, contact and via layers |
Jul. 22, 2003 |
| 6597028 |
Capacitively coupled ferroelectric random access memory cell and a method for manufacturing the same |
Jul. 22, 2003 |
| 6597045 |
Semiconductor raised source-drain structure |
Jul. 22, 2003 |
| 6594813 |
Cell architecture with local interconnect and method for making same |
Jul. 15, 2003 |
| 6593190 |
Non-volatile memory device having a bit line contact pad and method for manufacturing the same |
Jul. 15, 2003 |
| 6593609 |
Semiconductor memory device |
Jul. 15, 2003 |
| 6593632 |
Interconnect methodology employing a low dielectric constant etch stop layer |
Jul. 15, 2003 |
| 6594172 |
Method of selectively forming local interconnects using design rules |
Jul. 15, 2003 |
| 6589885 |
Semiconductor device and method in which contact hole is filled with silicon having low impurity concentration |
Jul. 8, 2003 |
| 6589886 |
Method for manufacturing aluminum oxide film for use in a semiconductor device |
Jul. 8, 2003 |
| 6590246 |
Structures and methods for improved capacitor cells in integrated circuits |
Jul. 8, 2003 |
| 6590258 |
SIO stacked DRAM logic |
Jul. 8, 2003 |
| 6583042 |
Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry |
Jun. 24, 2003 |
| 6583478 |
Transfer circuit of semiconductor device and structure thereof |
Jun. 24, 2003 |
| 6579776 |
Method of manufacturing semiconductor device |
Jun. 17, 2003 |
| 6576510 |
Method of producing a semiconductor memory device using a self-alignment process |
Jun. 10, 2003 |
| 6576544 |
Local interconnect |
Jun. 10, 2003 |
| 6576941 |
Ferroelectric capacitors on protruding portions of conductive plugs having a smaller cross-sectional size than base portions thereof |
Jun. 10, 2003 |
| 6573111 |
Method of making a semiconductor device with capacitor element |
Jun. 3, 2003 |
| 6573548 |
DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same |
Jun. 3, 2003 |
| 6569758 |
Sub-milliohm on-chip interconnection |
May. 27, 2003 |
| 6570232 |
Local interconnect structure for integrated circuit devices, source structure for the same, and method for fabricating the same |
May. 27, 2003 |
| 6566755 |
Method of forming a high surface area interconnection structure |
May. 20, 2003 |
| 6566759 |
Self-aligned contact areas for sidewall image transfer formed conductors |
May. 20, 2003 |
| 6563179 |
MOS transistor and method for producing the transistor |
May. 13, 2003 |
| 6563220 |
Method for forming conductors in semiconductor devices |
May. 13, 2003 |
| 6559043 |
Method for electrical interconnection employing salicide bridge |
May. 6, 2003 |
| 6559053 |
Method of passivating an oxide surface subjected to a conductive material anneal |
May. 6, 2003 |
| 6555450 |
Contact forming method for semiconductor device |
Apr. 29, 2003 |
| 6555455 |
Methods of passivating an oxide surface subjected to a conductive material anneal |
Apr. 29, 2003 |
| 6555478 |
Stacked local interconnect structure and method of fabricating same |
Apr. 29, 2003 |
| 6555915 |
Integrated circuit having interconnect to a substrate and method therefor |
Apr. 29, 2003 |
| 6548362 |
Method of forming MOSFET with buried contact and air-gap gate structure |
Apr. 15, 2003 |
| 6548390 |
SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMOR |
Apr. 15, 2003 |
| 6548394 |
Method of forming contact plugs |
Apr. 15, 2003 |
| 6548871 |
Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer |
Apr. 15, 2003 |
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