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Class Information
Number: 257/E21.59
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Local interconnects; local pads (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C10.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6693025 |
Local interconnect structures for integrated circuits and methods for making the same |
Feb. 17, 2004 |
| 6693335 |
Semiconductor raised source-drain structure |
Feb. 17, 2004 |
| 6689654 |
Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad |
Feb. 10, 2004 |
| 6689655 |
Method for production process for the local interconnection level using a dielectric conducting pair on pair |
Feb. 10, 2004 |
| 6686633 |
Semiconductor device, memory cell, and processes for forming them |
Feb. 3, 2004 |
| 6686636 |
Semiconductor raised source-drain structure |
Feb. 3, 2004 |
| 6683339 |
Semiconductor memory device having metal contact structure |
Jan. 27, 2004 |
| 6683355 |
Semiconductor raised source-drain structure |
Jan. 27, 2004 |
| 6680514 |
Contact capping local interconnect |
Jan. 20, 2004 |
| 6680538 |
Semiconductor device for suppressing detachment of conductive layer |
Jan. 20, 2004 |
| 6677211 |
Method for eliminating polysilicon residue |
Jan. 13, 2004 |
| 6677636 |
Structure for reducing contact aspect ratios |
Jan. 13, 2004 |
| 6677650 |
Silicon plugs and local interconnect for embedded memory and system-on-chip (SOC) applications |
Jan. 13, 2004 |
| 6670238 |
Method and structure for reducing contact aspect ratios |
Dec. 30, 2003 |
| 6670663 |
DRAM cell capacitor and manufacturing method thereof |
Dec. 30, 2003 |
| 6670713 |
Method for forming conductors in semiconductor devices |
Dec. 30, 2003 |
| 6664585 |
Semiconductor memory device having multilayered storage node contact plug and method for fabricating the same |
Dec. 16, 2003 |
| 6664639 |
Contact and via structure and method of fabrication |
Dec. 16, 2003 |
| 6661048 |
Semiconductor memory device having self-aligned wiring conductor |
Dec. 9, 2003 |
| 6656790 |
Method for manufacturing a semiconductor device including storage nodes of capacitor |
Dec. 2, 2003 |
| 6656794 |
Method of manufacturing semiconductor device including a memory area and a logic circuit area |
Dec. 2, 2003 |
| 6656806 |
SOI structure and method of producing same |
Dec. 2, 2003 |
| 6656825 |
Semiconductor device having an improved local interconnect structure and a method for forming such a device |
Dec. 2, 2003 |
| 6656853 |
Enhanced deposition control in fabricating devices in a semiconductor wafer |
Dec. 2, 2003 |
| 6653221 |
Method of forming a ground in SOI structures |
Nov. 25, 2003 |
| 6653241 |
Methods of forming protective segments of material, and etch stops |
Nov. 25, 2003 |
| 6653680 |
Storage electrode including tungsten silicide wall and large grained wall |
Nov. 25, 2003 |
| 6653733 |
Conductors in semiconductor devices |
Nov. 25, 2003 |
| 6654295 |
Reduced topography DRAM cell fabricated using a modified logic process and method for operating same |
Nov. 25, 2003 |
| 6649483 |
Method for fabricating a capacitor configuration |
Nov. 18, 2003 |
| 6649955 |
Ferroelectric memory device and method of fabricating the same |
Nov. 18, 2003 |
| 6645849 |
Method for manufacturing semiconductor device for suppressing detachment of conductive layer |
Nov. 11, 2003 |
| 6642098 |
DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same |
Nov. 4, 2003 |
| 6642118 |
Method for eliminating polysilicon residue by fully converting the polysilicon into silicon dioxide |
Nov. 4, 2003 |
| 6638805 |
Method of fabricating a DRAM semiconductor device |
Oct. 28, 2003 |
| 6638842 |
Methods of fabricating integrated circuitry |
Oct. 28, 2003 |
| 6639319 |
Conductive structure in an integrated circuit |
Oct. 28, 2003 |
| 6635522 |
Method of forming a MOS transistor in a semiconductor device and a MOS transistor fabricated thereby |
Oct. 21, 2003 |
| 6635966 |
Method for fabricating SRAM cell |
Oct. 21, 2003 |
| 6632731 |
Structure and method of making a sub-micron MOS transistor |
Oct. 14, 2003 |
| 6630380 |
Method for making three-dimensional metal-insulator-metal capacitors for dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM) |
Oct. 7, 2003 |
| 6630710 |
Elevated channel MOSFET |
Oct. 7, 2003 |
| 6630718 |
Transistor gate and local interconnect |
Oct. 7, 2003 |
| 6627462 |
Semiconductor device having a capacitor and method for the manufacture thereof |
Sep. 30, 2003 |
| 6627484 |
Method of forming a buried interconnect on a semiconductor on insulator wafer and a device including a buried interconnect |
Sep. 30, 2003 |
| 6627496 |
Process for producing structured layers, process for producing components of an integrated circuit, and process for producing a memory configuration |
Sep. 30, 2003 |
| 6624024 |
Method and apparatus for a flash memory device comprising a source local interconnect |
Sep. 23, 2003 |
| 6624029 |
Method of fabricating a self-aligned non-volatile memory cell |
Sep. 23, 2003 |
| 6620698 |
Method of manufacturing a flash memory |
Sep. 16, 2003 |
| 6620734 |
Methods of forming protective segments of material, and etch stops |
Sep. 16, 2003 |
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