Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Local interconnects; local pads (epo) > Patents

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Patent Number	Title Of Patent	Date Issued
4544941	Semiconductor device having multiple conductive layers and the method of manufacturing the semiconductor device	Oct. 1, 1985
4478679	Self-aligning process for placing a barrier metal over the source and drain regions of MOS semiconductors	Oct. 23, 1984
4470852	Method of making CMOS device and contacts therein by enhanced oxidation of selectively implanted regions	Sep. 11, 1984
4436582	Multilevel metallization process for integrated circuits	Mar. 13, 1984
4322736	Short-resistant connection of polysilicon to diffusion	Mar. 30, 1982
4306915	Method of making electrode wiring regions and impurity doped regions self-aligned therefrom	Dec. 22, 1981