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Class Information
Number: 257/E21.59
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Local interconnects; local pads (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C10.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5444018 |
Metallization process for a semiconductor device |
Aug. 22, 1995 |
| 5444022 |
Method of fabricating an interconnection structure for an integrated circuit |
Aug. 22, 1995 |
| 5439839 |
Self-aligned source/drain MOS process |
Aug. 8, 1995 |
| 5427980 |
Method of making a contact of a semiconductor memory device |
Jun. 27, 1995 |
| 5422308 |
Method of fabricating a tungsten contact |
Jun. 6, 1995 |
| 5419807 |
Method of providing electrical interconnect between two layers within a silicon substrate, semiconductor apparatus, and method of forming apparatus for testing semiconductor circuitry for oper |
May. 30, 1995 |
| 5420071 |
Methods of forming local interconnections in semiconductor devices |
May. 30, 1995 |
| 5410185 |
Internal bridging contact |
Apr. 25, 1995 |
| 5407859 |
Field effect transistor with landing pad |
Apr. 18, 1995 |
| 5407866 |
Method for forming a dielectric layer on a high temperature metal layer |
Apr. 18, 1995 |
| 5397722 |
Process for making self-aligned source/drain polysilicon or polysilicide contacts in field effect transistors |
Mar. 14, 1995 |
| 5376577 |
Method of forming a low resistive current path between a buried contact and a diffusion region |
Dec. 27, 1994 |
| 5376585 |
Method for forming titanium tungsten local interconnect for integrated circuits |
Dec. 27, 1994 |
| 5356833 |
Process for forming an intermetallic member on a semiconductor substrate |
Oct. 18, 1994 |
| 5348903 |
Process for fabricating a semiconductor memory cell having thin-film driver transistors overlapping dual wordlines |
Sep. 20, 1994 |
| 5349229 |
Local interconnect for integrated circuits |
Sep. 20, 1994 |
| 5346836 |
Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects |
Sep. 13, 1994 |
| 5340774 |
Semiconductor fabrication technique using local planarization with self-aligned transistors |
Aug. 23, 1994 |
| 5338702 |
Method for fabricating tungsten local interconnections in high density CMOS |
Aug. 16, 1994 |
| 5332913 |
Buried interconnect structure for semiconductor devices |
Jul. 26, 1994 |
| 5330640 |
Portable water filter having an inlet conduit with a weight and float construction |
Jul. 19, 1994 |
| 5326722 |
Polysilicon contact |
Jul. 5, 1994 |
| 5320971 |
Process for obtaining high barrier Schottky diode and local interconnect |
Jun. 14, 1994 |
| 5318924 |
Nitridation of titanium-tungsten interconnects |
Jun. 7, 1994 |
| 5317197 |
Semiconductor device |
May. 31, 1994 |
| 5315150 |
Semiconductor device and method of manufacturing the same |
May. 24, 1994 |
| 5306667 |
Process for forming a novel buried interconnect structure for semiconductor devices |
Apr. 26, 1994 |
| 5305256 |
Semiconductor memory device having stacked capacitor cell |
Apr. 19, 1994 |
| 5302539 |
VLSI interconnect method and structure |
Apr. 12, 1994 |
| 5278098 |
Method for self-aligned polysilicon contact formation |
Jan. 11, 1994 |
| 5272103 |
DRAM having a large dielectric breakdown voltage between an adjacent conductive layer and a capacitor electrode and method of manufacture thereof |
Dec. 21, 1993 |
| 5266156 |
Methods of forming a local interconnect and a high resistor polysilicon load by reacting cobalt with polysilicon |
Nov. 30, 1993 |
| 5266523 |
Method of forming self-aligned contacts using the local oxidation of silicon |
Nov. 30, 1993 |
| 5246876 |
Low cost polysilicon active P-channel load |
Sep. 21, 1993 |
| 5247198 |
Semiconductor integrated circuit device with multiplayered wiring |
Sep. 21, 1993 |
| 5232863 |
Method of forming electrical contact between a field effect transistor gate and a remote active area |
Aug. 3, 1993 |
| 5229307 |
Method of making extended silicide and external contact |
Jul. 20, 1993 |
| 5227319 |
Method of manufacturing a semiconductor device |
Jul. 13, 1993 |
| 5227333 |
Local interconnection having a germanium layer |
Jul. 13, 1993 |
| 5225699 |
DRAM having a large dielectric breakdown voltage between an adjacent conductive layer and a capacitor electrode and method of manufacture thereof |
Jul. 6, 1993 |
| 5212399 |
Low cost polysilicon active p-channel load |
May. 18, 1993 |
| 5190893 |
Process for fabricating a local interconnect structure in a semiconductor device |
Mar. 2, 1993 |
| 5187122 |
Process for fabricating an integrated circuit using local silicide interconnection lines |
Feb. 16, 1993 |
| 5173450 |
Titanium silicide local interconnect process |
Dec. 22, 1992 |
| 5169802 |
Internal bridging contact |
Dec. 8, 1992 |
| 5166771 |
Self-aligning contact and interconnect structure |
Nov. 24, 1992 |
| 5164331 |
Method of forming and etching titanium-tungsten interconnects |
Nov. 17, 1992 |
| 5162259 |
Method for forming a buried contact in a semiconductor device |
Nov. 10, 1992 |
| 5124280 |
Local interconnect for integrated circuits |
Jun. 23, 1992 |
| 5124774 |
Compact SRAM cell layout |
Jun. 23, 1992 |
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