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Class Information
Number: 257/E21.59
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Local interconnects; local pads (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C10.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5882992 |
Method for fabricating Tungsten local interconnections in high density CMOS circuits |
Mar. 16, 1999 |
| 5879998 |
Adaptively controlled, self-aligned, short channel device and method for manufacturing same |
Mar. 9, 1999 |
| 5880020 |
Method of making a semiconductor device having local connections formed by conductive plugs |
Mar. 9, 1999 |
| 5872033 |
Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch |
Feb. 16, 1999 |
| 5869391 |
Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry |
Feb. 9, 1999 |
| 5869787 |
Electrically conductive projections |
Feb. 9, 1999 |
| 5864155 |
Semiconductor array with self-adjusted contacts |
Jan. 26, 1999 |
| 5861676 |
Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit |
Jan. 19, 1999 |
| 5858845 |
Electrically conductive substrate interconnect continuity region and method of forming same with an angled implant |
Jan. 12, 1999 |
| 5851898 |
Method of forming stacked capacitor having corrugated side-wall structure |
Dec. 22, 1998 |
| 5849633 |
Electrically conductive projections and semiconductor processing method of forming same |
Dec. 15, 1998 |
| 5850096 |
Enhanced semiconductor integrated circuit device with a memory array and a peripheral circuit |
Dec. 15, 1998 |
| 5847463 |
Local interconnect comprising titanium nitride barrier layer |
Dec. 8, 1998 |
| 5843841 |
Fabrication process of a semiconductor integrated circuit device having a local interconnect pattern and a semiconductor integrated circuit device fabricated according to such a fabrication pr |
Dec. 1, 1998 |
| 5844274 |
Semiconductor device including an element isolating film having a flat upper surface |
Dec. 1, 1998 |
| 5840618 |
Method of manufacturing semiconductor device using an amorphous material |
Nov. 24, 1998 |
| 5838605 |
Iridium oxide local interconnect |
Nov. 17, 1998 |
| 5834370 |
Manufacture of semiconductor device containing polycide electrode |
Nov. 10, 1998 |
| 5830797 |
Interconnect methods and apparatus |
Nov. 3, 1998 |
| 5831305 |
CMOS devices having minimized drain contact area |
Nov. 3, 1998 |
| 5827764 |
Method for reducing the contact resistance of a butt contact |
Oct. 27, 1998 |
| 5827768 |
Method for manufacturing an MOS transistor having a self-aligned and planarized raised source/drain structure |
Oct. 27, 1998 |
| 5825074 |
Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry |
Oct. 20, 1998 |
| 5821165 |
Method of fabricating semiconductor devices |
Oct. 13, 1998 |
| 5817574 |
Method of forming a high surface area interconnection structure |
Oct. 6, 1998 |
| 5814541 |
Method for manufacturing semiconductor device |
Sep. 29, 1998 |
| 5814886 |
Semiconductor device having local connections formed by conductive plugs and method of making the same |
Sep. 29, 1998 |
| 5807779 |
Method of making tungsten local interconnect using a silicon nitride capped self-aligned contact process |
Sep. 15, 1998 |
| 5808855 |
Stacked container capacitor using chemical mechanical polishing |
Sep. 15, 1998 |
| 5801095 |
Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology |
Sep. 1, 1998 |
| 5795820 |
Method for simplifying the manufacture of an interlayer dielectric stack |
Aug. 18, 1998 |
| 5793111 |
Barrier and landing pad structure in an integrated circuit |
Aug. 11, 1998 |
| 5789303 |
Method of adding on chip capacitors to an integrated circuit |
Aug. 4, 1998 |
| 5780347 |
Method of forming polysilicon local interconnects |
Jul. 14, 1998 |
| 5773310 |
Method for fabricating a MOS transistor |
Jun. 30, 1998 |
| 5736421 |
Semiconductor device and associated fabrication method |
Apr. 7, 1998 |
| 5736770 |
Semiconductor device with conductive connecting layer and abutting insulator section made of oxide of same material |
Apr. 7, 1998 |
| 5728596 |
Method for forming a semiconductor buried contact with a removable spacer |
Mar. 17, 1998 |
| 5723910 |
Semiconductor device having a MOS structure |
Mar. 3, 1998 |
| 5721146 |
Method of forming buried contact architecture within a trench |
Feb. 24, 1998 |
| 5717236 |
Semiconductor memory including stacked capacitor having a flat surface |
Feb. 10, 1998 |
| 5717242 |
Integrated circuit having local interconnect for reduing signal cross coupled noise |
Feb. 10, 1998 |
| 5710067 |
Silicon oxime film |
Jan. 20, 1998 |
| 5708559 |
Precision analog metal-metal capacitor |
Jan. 13, 1998 |
| 5705427 |
Method of forming a landing pad structure in an integrated circuit |
Jan. 6, 1998 |
| 5702979 |
Method of forming a landing pad structure in an integrated circuit |
Dec. 30, 1997 |
| 5696014 |
Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch |
Dec. 9, 1997 |
| 5691212 |
MOS device structure and integration method |
Nov. 25, 1997 |
| 5691250 |
Method of forming a metal contact to a novel polysilicon contact extension |
Nov. 25, 1997 |
| 5686761 |
Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology |
Nov. 11, 1997 |
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