Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Local interconnects; local pads (epo) > Patents

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Class Information
Number: 257/E21.59
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Local interconnects; local pads (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C10.

Patents under this class:

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Patent Number	Title Of Patent	Date Issued
6121135	Modified buried contact process for IC device fabrication	Sep. 19, 2000
6121663	Local interconnects for improved alignment tolerance and size reduction	Sep. 19, 2000
6117754	Trench free process for SRAM with buried contact structure	Sep. 12, 2000
6117757	Method of forming landing pads for bit line and node contact	Sep. 12, 2000
6117761	Self-aligned silicide strap connection of polysilicon layers	Sep. 12, 2000
6117762	Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering	Sep. 12, 2000
6114199	Manufacturing method for ferroelectric film and nonvolatile memory using the same	Sep. 5, 2000
6107189	Method of making a local interconnect using spacer-masked contact etch	Aug. 22, 2000
6103569	Method for planarizing local interconnects	Aug. 15, 2000
6103586	Method for making integrated circuit capacitor including anchored plugs	Aug. 15, 2000
6103621	Silicide process for mixed mode product with dual layer capacitor which is protected by a capacitor protective oxide during silicidation of FET device	Aug. 15, 2000
6103622	Silicide process for mixed mode product with dual layer capacitor and polysilicon resistor which is protected with a capacitor protective oxide during silicidation of FET device	Aug. 15, 2000
6100126	Method of making a resistor utilizing a polysilicon plug formed with a high aspect ratio	Aug. 8, 2000
6100172	Method for forming a horizontal surface spacer and devices formed thereby	Aug. 8, 2000
6100185	Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line	Aug. 8, 2000
6100200	Sputtering process for the conformal deposition of a metallization or insulating layer	Aug. 8, 2000
6096633	Dual damascene process for forming local interconnect	Aug. 1, 2000
6096639	Method of forming a local interconnect by conductive layer patterning	Aug. 1, 2000
6096643	Method of fabricating a semiconductor device having polysilicon line with extended silicide layer	Aug. 1, 2000
6093596	Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry	Jul. 25, 2000
6093602	Method to form polycide local interconnects between narrowly-spaced features while eliminating stringers	Jul. 25, 2000
6093609	Method for forming semiconductor device with common gate, source and well	Jul. 25, 2000
6093619	Method to form trench-free buried contact in process with STI technology	Jul. 25, 2000
6093643	Electrically conductive projections and semiconductor processing method of forming same	Jul. 25, 2000
6093963	Dual landing pad structure including dielectric pocket	Jul. 25, 2000
6090673	Device contact structure and method for fabricating same	Jul. 18, 2000
6090695	Method for forming self-aligned landing pads	Jul. 18, 2000
6091117	Field effect transistor having elevated source and drain regions and methods of manufacturing the same	Jul. 18, 2000
6091129	Self-aligned trench isolated structure	Jul. 18, 2000
6087272	Method of producing thin film transistor	Jul. 11, 2000
6087275	Reduction of n-channel parasitic transistor leakage by using low power/low pressure phosphosilicate glass	Jul. 11, 2000
6083827	Method for fabricating local interconnect	Jul. 4, 2000
6083847	Method for manufacturing local interconnect	Jul. 4, 2000
6084279	Semiconductor device having a metal containing layer overlying a gate dielectric	Jul. 4, 2000
6080647	Process to form a trench-free buried contact	Jun. 27, 2000
6081016	CMOS device with improved wiring density	Jun. 27, 2000
6077755	Method for constructing multiple container capacitor	Jun. 20, 2000
6074938	Method of forming a semiconductor device comprising a dummy polysilicon gate electrode short-circuited to a dummy element region in a substrate	Jun. 13, 2000
6074960	Method and composition for selectively etching against cobalt silicide	Jun. 13, 2000
6071784	Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss	Jun. 6, 2000
6071798	Method for fabricating buried contacts	Jun. 6, 2000
6063676	Mosfet with raised source and drain regions	May. 16, 2000
6060389	Semiconductor fabrication employing a conformal layer of CVD deposited TiN at the periphery of an interconnect	May. 9, 2000
6060393	Deposition control of stop layer and dielectric layer for use in the formation of local interconnects	May. 9, 2000
6060404	In-situ deposition of stop layer and dielectric layer during formation of local interconnects	May. 9, 2000
6057571	High aspect ratio, metal-to-metal, linear capacitor for an integrated circuit	May. 2, 2000
6057583	Transistor with low resistance metal source and drain vertically displaced from the channel	May. 2, 2000
6054385	Elevated local interconnect and contact structure	Apr. 25, 2000
6051473	Fabrication of raised source-drain transistor devices	Apr. 18, 2000
6048785	Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching	Apr. 11, 2000