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Class Information
Number: 257/E21.59
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Local interconnects; local pads (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C10.


Patents under this class:
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Patent Number Title Of Patent Date Issued
6174822 Semiconductor device and method for fabricating the same Jan. 16, 2001
6168959 Method of forming a ferroelectric memory device Jan. 2, 2001
6168990 Method for fabricating Dram cell capacitor Jan. 2, 2001
6168991 DRAM capacitor including Cu plug and Ta barrier and method of forming Jan. 2, 2001
6169005 Formation of junctions by diffusion from a doped amorphous silicon film during silicidation Jan. 2, 2001
6169020 Methods of fabricating integrated circuits including metal silicide contacts extending between a gate electrode and a source/drain region Jan. 2, 2001
6165840 Method for fabricating a DRAM cell capacitor including forming first multilayer insulator, forming conductive plug, forming second insulator, and etching second and first insulators to form th Dec. 26, 2000
6165865 Method of fabricating dual cylindrical capacitor Dec. 26, 2000
6165900 Method for manufacturing semiconductor device Dec. 26, 2000
6166428 Formation of a barrier layer for tungsten damascene interconnects by nitrogen implantation of amorphous silicon or polysilicon Dec. 26, 2000
6162649 Method of manufacturing ferroelectric memory device Dec. 19, 2000
6162690 Methods of forming field effect transistors having self-aligned intermediate source and drain contacts Dec. 19, 2000
6159839 Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections Dec. 12, 2000
6159843 Method of fabricating landing pad Dec. 12, 2000
6160296 Titanium nitride interconnects Dec. 12, 2000
6157068 Semiconductor device with local interconnect of metal silicide Dec. 5, 2000
6156630 Titanium boride gate electrode and interconnect and methods regarding same Dec. 5, 2000
6156632 Method of forming polycide structures Dec. 5, 2000
6156634 Method of fabricating local interconnect Dec. 5, 2000
6153498 Method of fabricating a buried contact Nov. 28, 2000
6150216 Method for forming an electrode of semiconductor device capacitor Nov. 21, 2000
6150228 Method of manufacturing an SRAM with increased resistance length Nov. 21, 2000
6150266 Local interconnect formed using silicon spacer Nov. 21, 2000
6150267 Method of manufacturing buried contact in SRAM Nov. 21, 2000
6146940 Method of fabricating a dynamic random access memory device Nov. 14, 2000
6146954 Minimizing transistor size in integrated circuits Nov. 14, 2000
6146981 Method of manufacturing buried contact in SRAM Nov. 14, 2000
6147406 Electrical connection between an electrically conductive line and a node location, and integrated circuitry Nov. 14, 2000
6143593 Elevated channel MOSFET Nov. 7, 2000
6143595 Method for forming buried contact Nov. 7, 2000
6143602 Methods of forming memory device storage capacitors using protruding contact plugs Nov. 7, 2000
RE36938 Method of forming a landing pad structure in an integrated circuit Oct. 31, 2000
6140171 FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication Oct. 31, 2000
6140216 Post etch silicide formation using dielectric etchback after global planarization Oct. 31, 2000
6140672 Ferroelectric field effect transistor having a gate electrode being electrically connected to the bottom electrode of a ferroelectric capacitor Oct. 31, 2000
6136701 Contact structure for semiconductor device and the manufacturing method thereof Oct. 24, 2000
6137126 Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer Oct. 24, 2000
6137175 Semiconductor device with multi-layer wiring Oct. 24, 2000
6133104 Method of eliminating buried contact trench in MOSFET devices with self-aligned silicide including a silicon connection to the buried contact region which comprises a doped silicon sidewall Oct. 17, 2000
6133620 Semiconductor device and process for fabricating the same Oct. 17, 2000
6130102 Method for forming semiconductor device including a dual inlaid structure Oct. 10, 2000
6130121 Method for fabricating a transistor Oct. 10, 2000
6127214 Contact gate structure and method Oct. 3, 2000
6127260 Method of forming a tee shaped tungsten plug structure to avoid high aspect ratio contact holes in embedded DRAM devices Oct. 3, 2000
6127270 Methods of forming refractory metal silicide components and methods of restricting silicon surface migration of a silicon structure Oct. 3, 2000
6127706 Trench-free buried contact for SRAM devices Oct. 3, 2000
6127712 Mosfet with buried contact and air-gap gate structure Oct. 3, 2000
6124182 Method of forming stacked capacitor Sep. 26, 2000
6120915 Methods of forming refractory metal silicide components and methods of restricting silicon surface migration of a silicon structure Sep. 19, 2000
6121082 Method of fabricating DRAM with novel landing pad process Sep. 19, 2000

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