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Class Information
Number: 257/E21.59
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Local interconnects; local pads (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C10.

Patents under this class:

Patent Number Title Of Patent Date Issued
8710658 Under bump passive components in wafer level packaging Apr. 29, 2014
8704343 Borderless interconnect line structure self-aligned to upper and lower level contact vias Apr. 22, 2014
8647973 Semiconductor device capable of reducing electrical defects and method of fabricating the same Feb. 11, 2014
8603910 Method of processing a contact pad Dec. 10, 2013
8598720 Semiconductor device and manufacturing method thereof Dec. 3, 2013
8586469 Metal layer end-cut flow Nov. 19, 2013
8575018 Semiconductor device and method of forming bump structure with multi-layer UBM around bump formation area Nov. 5, 2013
8569161 Semiconductor device with copper wirebond sites and methods of making same Oct. 29, 2013
8563430 Semiconductor integrated circuit and method for fabricating the same Oct. 22, 2013
8552562 Profiled contact for semiconductor device Oct. 8, 2013
8552559 Very thick metal interconnection scheme in IC chips Oct. 8, 2013
8525335 Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof Sep. 3, 2013
8501617 Semiconductor devices including a topmost metal layer with at least one opening and their methods of fabrication Aug. 6, 2013
8487376 High-voltage transistor architectures, processes of forming same, and systems containing same Jul. 16, 2013
8431446 Via formation for cross-point memory Apr. 30, 2013
8415663 System and method for test structure on a wafer Apr. 9, 2013
8405185 Semiconductor device and semiconductor module including the same Mar. 26, 2013
8383505 Solder ball contact susceptible to lower stress Feb. 26, 2013
8350385 Reduced bottom roughness of stress buffering element of a semiconductor component Jan. 8, 2013
8349666 Fused buss for plating features on a semiconductor die Jan. 8, 2013
8329572 Semiconductor device and method for fabricating the same Dec. 11, 2012
8324622 Method of repairing probe pads Dec. 4, 2012
8304912 Structure and method for MOSFET gate electrode landing pad Nov. 6, 2012
8274160 Active area bonding compatible high current structures Sep. 25, 2012
8269348 IC die including RDL capture pads with notch having bonding connectors or its UBM pad over the notch Sep. 18, 2012
8242613 Bond pad for semiconductor die Aug. 14, 2012
8242012 Integrated circuit structure incorporating a conductor layer with both top surface and sidewall passivation and a method of forming the integrated circuit structure Aug. 14, 2012
8153510 Semiconductor bond pad patterns and method of formation Apr. 10, 2012
8134241 Electronic elements and devices with trench under bond pad feature Mar. 13, 2012
8133808 Wafer level chip package and a method of fabricating thereof Mar. 13, 2012
8115321 Separate probe and bond regions of an integrated circuit Feb. 14, 2012
8114741 Oxygen-rich layers underlying BPSG Feb. 14, 2012
8102063 Pad structure with a nano-structured coating film Jan. 24, 2012
8076778 Method for preventing Al-Cu bottom damage using TiN liner Dec. 13, 2011
8072070 Low fabrication cost, fine pitch and high reliability solder bump Dec. 6, 2011
8067305 Electrically conductive structure on a semiconductor substrate formed from printing Nov. 29, 2011
8030211 Methods for forming bit line contacts and bit lines during the formation of a semiconductor device Oct. 4, 2011
7998852 Methods for forming an RF device with trench under bond pad feature Aug. 16, 2011
7952176 Integrated circuit packaging system and method of manufacture thereof May. 31, 2011
7935623 Semiconductor device and method for fabricating the same May. 3, 2011
7919839 Support structures for on-wafer testing of wafer-level packages and multiple wafer stacked structures Apr. 5, 2011
7902056 Plasma treated metal silicide layer formation Mar. 8, 2011
7888258 Forming method of electrode and manufacturing method of semiconductor device Feb. 15, 2011
7851346 Bonding metallurgy for three-dimensional interconnect Dec. 14, 2010
7838408 Semiconductor device, wafer and method of designing and manufacturing the same Nov. 23, 2010
7808117 Integrated circuit having pads and input/output (I/O) cells Oct. 5, 2010
7808077 Semiconductor device and method for fabricating the same Oct. 5, 2010
7745340 Method of clearing electrical contact pads in thin film sealed OLED devices Jun. 29, 2010
7741227 Process for structuring at least one year as well as electrical component with structures from the layer Jun. 22, 2010
7741171 Oxygen-rich layers underlying BPSG Jun. 22, 2010

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