Resources Contact Us Home
Browse by Category: Main > Physics
Class Information
Number: 257/E21.586
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Filling of holes, grooves, vias or trenches with conductive material (epo) > By selective deposition of conductive material in vias, e.g., selective chemical vapor deposition on semiconductor material, plating (epo)
Description: This subclass is indented under subclass E21.585. This subclass is substantially the same in scope as ECLA classification H01L21/768C4B.

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13

Patent Number Title Of Patent Date Issued
8703615 Copper electroplating process for uniform across wafer deposition and void free filling on ruthenium coated wafers Apr. 22, 2014
8691656 Methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM Apr. 8, 2014
8658478 Transistor structure for improved static control during formation of the transistor Feb. 25, 2014
8652966 Semiconductor device manufacturing method and semiconductor device Feb. 18, 2014
8647977 Methods of forming interconnects Feb. 11, 2014
8637996 Perforation patterned electrical interconnects Jan. 28, 2014
8629559 Stress reduction apparatus with an inverted cup-shaped layer Jan. 14, 2014
8624399 Semiconductor device and method of manufacturing semiconductor device Jan. 7, 2014
8624277 Display substrate and method of manufacturing the same Jan. 7, 2014
8609519 Combinatorial approach for screening of ALD film stacks Dec. 17, 2013
8609531 Methods of selectively forming ruthenium liner layer Dec. 17, 2013
8603913 Porous dielectrics K value restoration by thermal treatment and or solvent treatment Dec. 10, 2013
8598031 Reliable interconnect for semiconductor device Dec. 3, 2013
8586431 Three dimensional integration and methods of through silicon via creation Nov. 19, 2013
8580684 Contact elements of semiconductor devices comprising a continuous transition to metal lines of a metallization layer Nov. 12, 2013
8580687 Semiconductor structure and method for making same Nov. 12, 2013
8575028 Method and apparatus for filling interconnect structures Nov. 5, 2013
8569154 Three dimensional integration and methods of through silicon via creation Oct. 29, 2013
8531033 Contact plug structure, semiconductor device, and method for forming contact plug Sep. 10, 2013
8513124 Copper electroplating process for uniform across wafer deposition and void free filling on semi-noble metal coated wafers Aug. 20, 2013
8501620 Method for depositing tungsten film having low resistivity, low roughness and high reflectivity Aug. 6, 2013
8492252 Three dimensional integration and methods of through silicon via creation Jul. 23, 2013
8492260 Processes of forming an electronic device including a feature in a trench Jul. 23, 2013
8486832 Method for fabricating semiconductor device Jul. 16, 2013
8486827 Device of filling metal in through-via-hole of semiconductor wafer and method using the same Jul. 16, 2013
8471236 Flat lower bottom electrode for phase change memory cell Jun. 25, 2013
8466052 Method of fabricating semiconductor device having buried wiring Jun. 18, 2013
8461046 Process for producing a metallization level and a via level and corresponding integrated circuit Jun. 11, 2013
8450210 Sequential station tool for wet processing of semiconductor wafers May. 28, 2013
8450197 Contact elements of a semiconductor device formed by electroless plating and excess material removal with reduced sheer forces May. 28, 2013
8445380 Semiconductor having a high aspect ratio via May. 21, 2013
8435894 Depositing tungsten into high aspect ratio features May. 7, 2013
8420533 Metallization system of a semiconductor device comprising rounded interconnects formed by hard mask rounding Apr. 16, 2013
8415238 Three dimensional integration and methods of through silicon via creation Apr. 9, 2013
8415251 Electric component and component and method for the production thereof Apr. 9, 2013
8389406 Method of manufacturing semiconductor device Mar. 5, 2013
8377820 Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size Feb. 19, 2013
8367444 Display substrate and method of manufacturing the same Feb. 5, 2013
8361904 Semiconductor device having fine pattern wiring lines integrally formed with contact plug and method of manufacturing same Jan. 29, 2013
8349733 Manufacturing method of substrate with through electrode Jan. 8, 2013
8343791 Plating process and apparatus for through wafer features Jan. 1, 2013
8343866 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region Jan. 1, 2013
8328156 Techniques for forming solder bump interconnects Dec. 11, 2012
8324097 Method of forming a copper topped interconnect structure that has thin and thick copper traces Dec. 4, 2012
8298946 Method of selective coating of a composite surface production of microelectronic interconnections using said method and integrated circuits Oct. 30, 2012
8298948 Capping of copper interconnect lines in integrated circuit devices Oct. 30, 2012
8293577 Semiconductor package and method of manufacturing the same Oct. 23, 2012
8283650 Flat lower bottom electrode for phase change memory cell Oct. 9, 2012
8278216 Selective capping of copper Oct. 2, 2012
8278220 Method to direct pattern metals on a substrate Oct. 2, 2012

1 2 3 4 5 6 7 8 9 10 11 12 13

  Recently Added Patents
Digital fine delay processing
System and method for redundant array copy removal in a pointer-free language
Prioritizing application data for transmission in a wireless user device
Display device substrate, method for manufacturing the same, display device, method for forming multi-layer wiring, and multi-layer wiring substrate
Using location based services for determining a calling window
Notification systems and methods that consider traffic flow predicament data
In-vehicle communication system and method of operation
  Randomly Featured Patents
Electrical connector with stress-distribution features
Guide tab and slide incorporating the same
In-service test valve
Printing in a secure environment
Control system for controlling the output power of a power train
Adaptive spin latches
Method for mounting a heavy equipment on a ship's hull
Method of manufacturing a semicondutor integrated circuit device having nonvolatile memory cells
Key management protocol and authentication system for secure internet protocol rights management architecture
Variable resistance exercise apparatus