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Class Information
Number: 257/E21.585
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Filling of holes, grooves, vias or trenches with conductive material (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C4.

Sub-classes under this class:

Class Number Class Name Patents
257/E21.587 By deposition over sacrificial masking layer, e.g., lift-off (epo) 162
257/E21.586 By selective deposition of conductive material in vias, e.g., selective chemical vapor deposition on semiconductor material, plating (epo) 641
257/E21.588 Reflowing or applying pressure to fill contact hole, e.g., to remove voids (epo) 236

Patents under this class:

Patent Number Title Of Patent Date Issued
8513119 Method of forming bump structure having tapered sidewalls for stacked dies Aug. 20, 2013
8513116 Atomic layer deposition of tungsten materials Aug. 20, 2013
8508051 Protection film having a plurality of openings above an electrode pad Aug. 13, 2013
8508050 Wiring substrate, semiconductor device, and method for manufacturing wiring substrate Aug. 13, 2013
8502308 Semiconductor device with a trench isolation and method of manufacturing trenches in a semiconductor body Aug. 6, 2013
8501606 Methods of forming wiring structures Aug. 6, 2013
8501587 Stacked integrated chips and methods of fabrication thereof Aug. 6, 2013
8497206 Method of processing backside copper layer for semiconductor chips Jul. 30, 2013
8497202 Interconnect structures and methods of manufacturing of interconnect structures Jul. 30, 2013
8492264 Method for forming interconnection levels of an integrated circuit Jul. 23, 2013
8486834 Method for manufacturing memory device Jul. 16, 2013
8486832 Method for fabricating semiconductor device Jul. 16, 2013
8482130 Interconnect structure comprising blind vias intended to be metalized Jul. 9, 2013
8476135 Integrated circuit packaging system with vertical interconnects and method of manufacture thereof Jul. 2, 2013
8466560 Dummy structures having a golden ratio and method for forming the same Jun. 18, 2013
8466069 Method for manufacturing semiconductor device Jun. 18, 2013
8466063 Integration of bottom-up metal film deposition Jun. 18, 2013
8466062 TSV backside processing using copper damascene interconnect technology Jun. 18, 2013
8466059 Multi-layer interconnect structure for stacked dies Jun. 18, 2013
8466006 Thermally insulated phase material cells Jun. 18, 2013
8461692 Semiconductor device structures including damascene trenches with conductive structures and related method Jun. 11, 2013
8461046 Process for producing a metallization level and a via level and corresponding integrated circuit Jun. 11, 2013
8461012 Device with ground plane for high frequency signal transmission and method therefor Jun. 11, 2013
8450172 Non-insulating stressed material layers in a contact level of semiconductor devices May. 28, 2013
8441111 Stub minimization for multi-die wirebond assemblies with parallel windows May. 14, 2013
8436473 Integrated circuits including air gaps around interconnect structures, and fabrication methods thereof May. 7, 2013
8435870 Method for manufacturing semiconductor device May. 7, 2013
8435860 Trench type semiconductor device and fabrication method for the same May. 7, 2013
8432038 Through-silicon via structure and a process for forming the same Apr. 30, 2013
8431479 Semiconductor devices having redistribution structures and packages, and methods of forming the same Apr. 30, 2013
8431457 Method for fabricating a shielded gate trench MOS with improved source pickup layout Apr. 30, 2013
8431421 Test patterns for detecting misalignment of through-wafer vias Apr. 30, 2013
8426919 Integrated circuitry Apr. 23, 2013
8420530 Nano-interconnects for atomic and molecular scale circuits Apr. 16, 2013
8415806 Semiconductor structure and method for manufacturing the same Apr. 9, 2013
8415804 Semiconductor chip, method of fabricating the same, and stack module and memory card including the same Apr. 9, 2013
8415721 Field side sub-bitline nor flash array and method of fabricating the same Apr. 9, 2013
8405185 Semiconductor device and semiconductor module including the same Mar. 26, 2013
8404588 Method of manufacturing via electrode Mar. 26, 2013
8399936 Through substrate via semiconductor components Mar. 19, 2013
8399930 Method of manufacturing a semiconductor device having a contact plug Mar. 19, 2013
8399351 Method of manufacturing a semiconductor device Mar. 19, 2013
8399327 Methods of manufacturing a semiconductor device Mar. 19, 2013
8391017 Thin-film capacitor structures embedded in semiconductor packages and methods of making Mar. 5, 2013
8390074 Structure and method for latchup improvement using through wafer via latchup guard ring Mar. 5, 2013
8389406 Method of manufacturing semiconductor device Mar. 5, 2013
8384224 Through wafer vias and method of making same Feb. 26, 2013
8383514 Method for stacking serially-connected integrated circuits and multi-chip device made from same Feb. 26, 2013
8372745 Semiconductor device, its manufacturing method, and sputtering target material for use in the method Feb. 12, 2013
8372739 Diffusion barrier for integrated circuits formed from a layer of reactive metal and method of fabrication Feb. 12, 2013

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