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Class Information
Number: 257/E21.585
Name: Active solid-state devices (e.g., transistors, solid-state diodes) > Processes or apparatus adapted for manufacture or treatment of semiconductor or solid-state devices or of parts thereof (epo) > Manufacture or treatment of devices consisting of plurality of solid-state components formed in or on common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof (epo) > Manufacture of specific parts of devices (epo) > Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (epo) > Characterized by formation and post treatment of dielectrics, e.g., planarizing (epo) > Filling of holes, grooves, vias or trenches with conductive material (epo)
Description: This subclass is indented under subclass E21.582. This subclass is substantially the same in scope as ECLA classification H01L21/768C4.










Sub-classes under this class:

Class Number Class Name Patents
257/E21.587 By deposition over sacrificial masking layer, e.g., lift-off (epo) 162
257/E21.586 By selective deposition of conductive material in vias, e.g., selective chemical vapor deposition on semiconductor material, plating (epo) 641
257/E21.588 Reflowing or applying pressure to fill contact hole, e.g., to remove voids (epo) 236


Patents under this class:
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Patent Number Title Of Patent Date Issued
RE38383 Method for forming a via plug in a semiconductor device Jan. 13, 2004
6677230 Method of manufacturing semiconductor device Jan. 13, 2004
6677232 Method for fabricating metal conductors and multi-level interconnects in a semiconductor device Jan. 13, 2004
6677233 Material deposition from a liquefied gas solution Jan. 13, 2004
6677632 Method of forming a metal to polysilicon contact in oxygen environment Jan. 13, 2004
6677682 Multilayer interconnection structure including an alignment mark Jan. 13, 2004
6675469 Vapor phase connection techniques Jan. 13, 2004
6673704 Semiconductor device and method of manufacturing the same Jan. 6, 2004
6673724 Pulsed-mode RF bias for side-wall coverage improvement Jan. 6, 2004
6670267 Formation of tungstein-based interconnect using thin physically vapor deposited titanium nitride layer Dec. 30, 2003
6670268 Metal interconnection with low resistance in a semiconductor device and a method of forming the same Dec. 30, 2003
6670682 Multilayered doped conductor Dec. 30, 2003
6666959 Semiconductor workpiece proximity plating methods and apparatus Dec. 23, 2003
6667228 Method for fabricating cell plugs of semiconductor device Dec. 23, 2003
6664185 Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect Dec. 16, 2003
6664585 Semiconductor memory device having multilayered storage node contact plug and method for fabricating the same Dec. 16, 2003
6664633 Alkaline copper plating Dec. 16, 2003
6664636 Cu film deposition equipment of semiconductor device Dec. 16, 2003
6660154 Seed layer Dec. 9, 2003
6660634 Method of forming reliable capped copper interconnects Dec. 9, 2003
6660636 Highly selective and complete interconnect metal line and via/contact hole filling by electroless plating Dec. 9, 2003
6661048 Semiconductor memory device having self-aligned wiring conductor Dec. 9, 2003
6656838 Process for producing semiconductor and apparatus for production Dec. 2, 2003
6657263 MOS transistors having dual gates and self-aligned interconnect contact windows Dec. 2, 2003
6657306 Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method Dec. 2, 2003
6653737 Interconnection structure and method for fabricating same Nov. 25, 2003
6653229 Integrated circuit with a recessed conductive layer Nov. 25, 2003
6649513 Copper back-end-of-line by electropolish Nov. 18, 2003
6645845 Methods of forming interconnect regions of integrated circuitry Nov. 11, 2003
6645849 Method for manufacturing semiconductor device for suppressing detachment of conductive layer Nov. 11, 2003
6645857 Key hole filling Nov. 11, 2003
6645858 Method of catalyzing copper deposition in a damascene structure by plasma treating the barrier layer and then applying a catalyst such as iodine or iodine compounds to the barrier layer Nov. 11, 2003
6645863 Method of manufacturing semiconductor device and semiconductor device Nov. 11, 2003
6641867 Methods for chemical vapor deposition of tungsten on silicon or dielectric Nov. 4, 2003
6638855 Method of filling contact hole of semiconductor device Oct. 28, 2003
6638856 Method of depositing metal onto a substrate Oct. 28, 2003
6639298 Multi-layer inductor formed in a semiconductor substrate Oct. 28, 2003
6638775 Method for fabricating semiconductor memory device Oct. 28, 2003
6635406 Method of producing vertical interconnects between thin film microelectronic devices and products comprising such vertical interconnects Oct. 21, 2003
6635528 Method of planarizing a conductive plug situated under a ferroelectric capacitor Oct. 21, 2003
6635965 Method for producing ultra-thin tungsten layers with improved step coverage Oct. 21, 2003
6632335 Plating apparatus Oct. 14, 2003
6630059 Workpeice proximity plating apparatus Oct. 7, 2003
6630360 Advanced process control (APC) of copper thickness for chemical mechanical planarization (CMP) optimization Oct. 7, 2003
6630741 Method of reducing electromigration by ordering zinc-doping in an electroplated copper-zinc interconnect and a semiconductor device thereby formed Oct. 7, 2003
6627537 Bit line and manufacturing method thereof Sep. 30, 2003
6627542 Continuous, non-agglomerated adhesion of a seed layer to a barrier layer Sep. 30, 2003
6627547 Hot metallization process Sep. 30, 2003
6624066 Reliable interconnects with low via/contact resistance Sep. 23, 2003
6624513 Semiconductor device with multilayer conductive structure formed on a semiconductor substrate Sep. 23, 2003

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